Coolquest, Inc.	Home	Products	Support	About	Contact
C++BOLD Reference Manual

10.4. Constraint Files for Programmable Devices

TXConstraints is a class that generates location constraint files in Xilinx® UCF format. TXConstraints is documented in file cb_xconstraints.h, provided in the CBOLD distribution.

An excerpt from cb_xconstraints.h:

// TXConstraints is a class that generates constraint files compatible with Xilinx UCF format.
// When GenerateConstraintsFile() is called, it is passed a target module (optional) and a target part.
// The generated constraint file contains pin location constraints for the target part.
// For each of the target module's PinSpec's (i.e., node of a port) GenerateConstraintFiles() traces the connection from the PinSpec to the target part.
// If the trace is successful, the pin name in the constraint file is derived from the target module's port name.
// If the trace fails for a particular PinSpec, the following is attempted if enabled:
// The connection is traced through certain parts, e.g., through a resistor that is connected between the PinSpec and the target part.
// If the trace still fails, the PinSpec is ignored, i.e., the PinSpec has no effect on the part's constraint file.
 
// Once all of the target module's PinSpec's are traced, GenerateConstraintsFile() checks that each of the target part's pins has a location constraint in the constraint file.
// If not, the following is attempted if enabled:
//   A location constraint is derived from the name (in the design's netlist) of the net attached to the pin (if any).
// Multi-pin nodes of the target part (e.g., power supply pins) never contribute to the constraints file.
 
// If enabled to do so, GenerateConstraintsFile() will modify pin names to eliminate duplicates, force pin names to uppercase, etc.
// If multiple PinSpecs of the target module connect to the same pin on the part, then multiple LOC constraints will be created.

The following excerpt from the IROD Example Design shows postprocessing code in main() that generates several constraint files.

int main(int argc, char* argv[])
{
  ...
  Log << "Creating constraint files";    // output constraint files
  TXConstraints Constraints;
 
  Constraints.AddIgnorePort( "VCC", "VB", "GND" );            // do not create location constraints for these ports
  Constraints.AddIgnorePort( "TCK", "TMS", "TDI", "TDO" );
  Constraints.AddIgnorePort( "CCLK", "DIN", "PROGRAM_N" );
  ...
  // VME PLDs
  Constraints.GenerateConstraintsFile( OUTPUT_BASE "_VMECPldConstraints.ucf", &Root.VME_Interface.VMEC_PLD,  &Root.VME_Interface.VMEC_PLD.Cpld       );
  Constraints.GenerateConstraintsFile( OUTPUT_BASE "_VMEDPldConstraints.ucf", &Root.VME_Interface.VMED_PLD,  &Root.VME_Interface.VMED_PLD.Cpld       );
  ...
  Constraints.SetPinPrefix( "P" );       // FPGA's in PQFP's require a P before the pin number
  // DX FPGAs
  Constraints.GenerateConstraintsFile( OUTPUT_BASE "_DXBFpgaConstraints.ucf", &Root.DataExchange.DXB_FPGA,   &Root.DataExchange.DXB_FPGA.Fpga.Fpga   );
  Constraints.GenerateConstraintsFile( OUTPUT_BASE "_DXFFpgaConstraints.ucf", &Root.DataExchange.DXF_FPGA_A, &Root.DataExchange.DXF_FPGA_A.Fpga.Fpga );
  ...
}

The arguments of GenerateConstraintsFile() are the destination file path and pointers to the target module (wrapper) and the target part.

The names of target module ports determine the names in the LOC constraints.
The pins of target part ports determine the pins in the LOC constraints.
TXConstraints uses the design's netlist to trace from target module ports to target part pins.
If the TraceThroughParts feature is enabled, TXConstraints will trace through one or more two-terminal parts, e.g., series termination resistors or AC coupling capacitors.

Here is one of the resulting constraint files: irod_VMECPldConstraints.ucf.