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C++BOLD Reference Manual

10.3. Selective Registration

A member is visible to the CBOLD framework only if it is registered. In some cases, the designer may deliberately instantiate a member but not register it.

The CRB Example Design uses selective registration when registering the RodSlot array. C++ array indexes are zero-based, but the CRB's RodSlot's are numbered 5-12 and 14-21. The designer could have implemented two eight-element arrays, one for RodSlot's 5-12 and another for 14-21, but translating the indexes and handling the two separate arrays would have been awkward.

Instead, the designer implemented a single 22-element array, but only registered elements 5-12 and 14-21. Because elements 0-4 and 13 are not registered, they are invisible to the CBOLD framework and do not affect the design.

The selective registration in the CRB example design is considered static, because the registering of the array is fixed at compile time. The IROD Example Design uses dynamic selective registration, in which the registering of some members is determined at run time.

Specifically, the IROD's CM_STD_FPGA class uses selective registration to register FPGA I/O ports and some passive components. The registration is dynamic, because it depends on whether the FPGA's VREF feature is used for each I/O bank. For each instance of CM_STD_FPGA, the user calls CM_STD_FPGA::UseVref() to specify which I/O banks will use VREF. For example:

class CM_BPI_FPGA : public TModule {    // BPI FPGA for Interconnect Subsystem
public:
  ...
// ***** member modules and parts ***** //
  CM_STD_FPGA  Fpga;
 
  virtual void Register() {
    ...
    Fpga.UseVref( 1, 2, 3, 4 );         // use VREF on banks 1, 2, 3, 4
    reg( Fpga );                        // register the FPGA after calling UseVref()
  }
  ...
};

CM_STD_FPGA::UseVref() does not perform any registering. It just sets private variables according to the user's request.

CM_STD_FPGA::Register() registers members according to the values in the private variables. For example, the I/O port for each bank that uses VREF is registered with a range reduced by three to allow for the three pins dedicated to VREF. Additionally, if any bank uses VREF, CM_STD_FPGA registers a resistor-divider and filter capacitor for establishing the reference voltage.

CM_STD_FPGA::Connect() will also use the private VREF variables to properly connect I/O pins to Bank ports and the resistor-divider to VREF pins.