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C++BOLD Example Design: IROD

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _DPU_ControlH_
#define _DPU_ControlH_
 
#include "jtag.h"
#include "dc_fpga.h"
 
// DPU Control subsystem
 
// This subsystem is basically just one FPGA.
// Logically, though, some of the subsystem is located in the DPU and HPU XB FPGA's.
 
// All necessary decoupling capacitors are already included.
 
 
// CB_Half_DC:  interface between HalfROD and DPU_Control
class CB_Half_DC : public TBundle {
public:
  port DCD;   // DC Data bus to DPU's
  port DCC;   // DC Control bus to DPU's
  virtual void Register() {
    regb( DCD, 31, 0 );
    regb( DCC, 10, 0 );
  }
};
 
// CB_Host_DC:  interface between HPU and DPU_Control
class CB_Host_DC : public TBundle {
public:
  port DCD_H;   // DC Data bus to HPU
  port DCC_H;   // DC Control bus to HPU
  virtual void Register() {
    regb( DCD_H, 31, 0 );
    regb( DCC_H, 15, 0 );
  }
};
 
 
 
class CM_DPU_Control : public TModule {    // DPU Control Subsystem
public:
// ***** member bundles ***** //
  CB_DC_CG    CG;  // interface to ClockGeneration
  CB_Half_DC  A;   // interface to Half A
  CB_Half_DC  B;   // interface to Half B
  CB_Host_DC  HO;  // interface to Host
  CB_DC_JT    JT;  // interface to JTAG
 
 
// ***** member ports ***** //
  port MB_VCC;      // 3.3V
  port MB_VB;       // 2.5V for FPGA internal
  port GND;
 
 
// ***** member modules and parts ***** //
  CM_DC_FPGA  DC_FPGA;
 
// pullups for OR-tie
// given the large resistor values, OR-tied signals are essentially asynchronous:
//    R      DPU   DC_FPGA       I/O    trace
//   360 * (  6  +    1    ) * ( 10 pf + 10 pf)   =   50 ns
  CP_R360    PullupDCC_A10;
  CP_R360    PullupDCC_A9;
  CP_R360    PullupDCC_B10;
  CP_R360    PullupDCC_B9;
 
 
  virtual void Register() {
// bundles
    reg( CG );
    reg( A  );
    reg( B  );
    reg( HO );
    reg( JT );
 
// ports
    reg( MB_VCC );
    reg( MB_VB  );
    reg( GND );
 
// parts and modules
    reg( DC_FPGA );
 
    reg( PullupDCC_A10 );
    reg( PullupDCC_A9  );
    reg( PullupDCC_B10 );
    reg( PullupDCC_B9  );
  }
 
  virtual void Connect() {
    wire( MB_VCC, "VCC" );
    wire( MB_VB,  "VB"  );
    wireall( GND );
 
    JT.DC_FPGA  <<  DC_FPGA.JTAG_CONF;
 
    wire( CG, DC_FPGA );   // clocks
 
    DC_FPGA.DCC_A( 10 )  ^  PullupDCC_A10  ^  MB_VCC;
    DC_FPGA.DCC_A(  9 )  ^  PullupDCC_A9   ^  MB_VCC;
 
    DC_FPGA.DCC_B( 10 )  ^  PullupDCC_B10  ^  MB_VCC;
    DC_FPGA.DCC_B(  9 )  ^  PullupDCC_B9   ^  MB_VCC;
 
    A.DCD     <<  DC_FPGA.DCD_A;
    A.DCC     <<  DC_FPGA.DCC_A;
 
    B.DCD     <<  DC_FPGA.DCD_B;
    B.DCC     <<  DC_FPGA.DCC_B;
 
    HO.DCD_H  <<  DC_FPGA.DCD_H;      // DCD_H and DCC_H are not quite analogous to A/B's DCD and DCC
    HO.DCC_H  <<  DC_FPGA.DCC_H;
 
  }
};
 
#endif