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C++BOLD Example Design: IROD

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _DC_FPGAH_
#define _DC_FPGAH_
 
#include "std_fpga.h"
 
 
// Data Exchange Front End FPGA
 
class CM_DC_FPGA : public TModule {
public:
// ***** member bundles ***** //
  CB_JTAG_CONF JTAG_CONF;
 
// ***** member ports ***** //
  port VCC;          // 3.3V
  port VB;           // 2.5V for FPGA internal
  port GND;
 
  port DX_CLK;   // possibly of little use to DC FPGA
  port DC_CLK;   // DC_CLK, RCLK, and SCLK are available to both DPU and HPU XB FPGA's
  port RCLK;
  port SCLK;
 
  port DCD_A;    // DC data and control busses to ROD halves A and B
  port DCC_A;
 
  port DCD_B;
  port DCC_B;
 
  port DCD_H;    // data and control busses to HPU's XB FPGA
  port DCC_H;
 
 
// ***** member modules and parts ***** //
  CM_STD_FPGA  Fpga;
 
  virtual void Register() {
// bundles
    reg(  JTAG_CONF );
 
// ports
    reg(   VCC );
    reg(   VB  );
    reg(   GND );
 
    reg(  DX_CLK );
    reg(  DC_CLK );
    reg(  RCLK   );
    reg(  SCLK   );
 
    regb( DCD_A, 31, 0 );
    regb( DCC_A, 10, 0 );
 
    regb( DCD_B, 31, 0 );
    regb( DCC_B, 10, 0 );
 
    regb( DCD_H, 31, 0 );
    regb( DCC_H, 15, 0 );
 
// parts and modules
//    Fpga.UseVref( ... );
    reg( Fpga );
  }
 
  virtual void Connect() {
 
    wire( VCC );
    wire( VB  );
    wire( GND );
 
    JTAG_CONF << Fpga.JTAG_CONF;
 
 // bus between all DX FPGA's
    DCD_H( 16,  0 )  <<  Fpga.Bank[ 3 ];             //  17   -->  0 remaining in bank 3
    DCD_H( 31, 17 )  <<  Fpga.Bank[ 2 ]( 14,  0 );   //  15   -->  2 remaining in bank 2
 
    "/NC"            <<  Fpga.Bank[ 2 ](     15 );   //   1   -->  1 remaining in bank 2
    "/NC"            <<  Fpga.Bank[ 2 ](     16 );   //   1   -->  0 remaining in bank 2
 
    DCC_H( 15,  8 )  <<  Fpga.Bank[ 1 ](  7,  0 );   //   8   --> 10 remaining in bank 1
    DCC_H(  7,  0 )  <<  Fpga.Bank[ 4 ]( 17, 10 );   //   8   --> 10 remaining in bank 4
 
 // bus to DPU's in half-ROD
    DCD_A(  9,  0 )  <<  Fpga.Bank[ 4 ](  0,  9 );   //  10 note inverted range  -->  0 remaining in bank 4
    DCD_A( 24, 10 )  <<  Fpga.Bank[ 5 ](  0, 14 );   //  15 note inverted range  -->  0 remaining in bank 5
    DCD_A( 31, 25 )  <<  Fpga.Bank[ 6 ]( 11, 17 );   //   7 note inverted range  --> 11 remaining in bank 6
 
    DCC_A( 10,  0 )  <<  Fpga.Bank[ 6 ](  0, 10 );   //  11 note inverted range  -->  0 remaining in bank 6
 
 
    DCD_B(  9,  0 )  <<  Fpga.Bank[ 1 ]( 17,  8 );   //  10   -->  0 remaining in bank 1
    DCD_B( 25, 10 )  <<  Fpga.Bank[ 0 ];             //  16   -->  0 remaining in bank 0
    DCD_B( 31, 26 )  <<  Fpga.Bank[ 7 ](  5,  0 );   //   6   --> 12 remaining in bank 7
 
    DCC_B            <<  Fpga.Bank[ 7 ]( 16,  6 );   //  11   -->  1 remaining in bank 7
 
    "/NC"            <<  Fpga.Bank[ 7 ]( 17 );       //   1   -->  0 remaining in bank 7
 
 
    RCLK     <<  Fpga.GCK( 0 );   // same GCK as on GPU XB FPGA
    SCLK     <<  Fpga.GCK( 1 );   // same GCK as on GPU XB FPGA
    DC_CLK   <<  Fpga.GCK( 2 );   // same GCK as on GPU XB FPGA
    DX_CLK   <<  Fpga.GCK( 3 );
 
  }
};
 
#endif