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C++BOLD Example Design: CRB

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _CrbH_
#define _CrbH_
 
#include "cb_base.h"
#include "cb_shorthand.h"
 
// above:  standard code
// below:  design-specific code
 
// Search all files for ">>>" to find important comments.
 
// file paths, etc
#define  DESIGN_NAME  "crb"                        // name of design--used primarily to form file names
//                    dir for all CBOLD output  subdir. for this design   base of file name
#define  OUTPUT_BASE  OUTPUT_PATH DIR_SEP       DESIGN_NAME DIR_SEP       DESIGN_NAME        // concatenation of path and name --> base for output file names
 
 
// CRB  ==  CSC ROD Backplane
// CSC  ==  Cathode Strip Chambers (for ATLAS Muon)
// ROD  ==  ReadOut Driver
// TIM  ==  TTC Interface Module
// TTC  ==  Timing, Trigger and Control (for ATLAS)
// IROD ==  Irvine ROD (designed at the University of California, Irvine)
 
// The CRB is a P5/P6/RP5/RP6 backplane that supports 16+ IROD's and one TIM

using std::setw;
using std::setfill;
 
// files needed by many of the subsystems
#include "crb_clones.h"     // cloned resisters, capacitors, etc.
#include "decoupling.h"
 
// subsystems
#include "crb_rod_slot.h"
#include "crb_tim_slot.h"
#include "crb_terminators.h"
#include "crb_power.h"

// ************  CRB  ************
// subsystem           abbreviation
// ------------        ------------
//   RodSlot             R05-R12, R14-R21
//   TimSlot             T13
//   Terminators         TM or Term
//   Power               PW

// Slots assignments:
//    Slot  ref. base  description
//     1-3             no connector, slots are reserved for 6U boards
//       4             no connector, slot   is reserved for 6U/9U separator
//    5-12   R05-R12   ROD slots
//      13       T13   TIM slot
//   14-21   R14-R21   ROD slots
 
 
 
class CM_Root : public TRootModule {
public:
// root-level module has no ports
 
// instantiate subsystems
  CM_RodSlot          RodSlot[ 22 ]; // only 16 of these are registered (5-12, 14-21) -- non-registered RodSlot's are ignored
  CM_TimSlot          TimSlot;
  CM_Terminators      Terminators;
  CM_Power            Power;
 

  virtual void Register() {

    for ( int i =  5; i <= 21; ++ i ) {           // for each slot
      if ( i == 13 ) {                            // TIM is in slot 13
        Reg( &TimSlot, "TimSlot", i );            // register TimSlot as TimSlot13
        TimSlot.SetReferenceBase( "T13" );        // use T13 as the base for all of its reference designators
        continue;
      }
      regn( RodSlot, i );                                                                   // register the RodSlot
      RodSlot[ i ].SetReferenceBase( CSTRING( "R" << setw( 2 ) << setfill( '0' ) << i ) );  // set its reference base
    }
 
//        subsystem                                              // reference base
//        -----------                                            --
    reg(  Terminators     );  Terminators.SetReferenceBase(     "TM" );
    reg(  Power           );  Power.SetReferenceBase(           "PW" );
  }
 
  virtual void Connect() {
 
// *** connect subsystem ports (except power ports) *** //

  // net names to override subsequently assigned net names
    "TTC_L" << TimSlot.Rod[  5 ].TTC;
    "TTC_R" << TimSlot.Rod[ 14 ].TTC;
 
  // connect ROD slots to TIM slot
    for ( int i = 5; i <= 21; ++i ) {             // for each slot
      if ( i == 13 )  continue;                   // skip Tim slot
      "R"  <<  TimSlot.Rod[ i ]  <<  RodSlot[ i ].Tim;
    }
 
  // connect terminators to TIM slot
    TimSlot.Term  <<  Terminators.Tim;

// *** connect supply ports ***
    wireall( "VCC5"  );
    wireall( "VCC3"  );
    wireall( "GND" );
  }
};
 
#endif