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// THIS FILE IS IN THE PUBLIC DOMAIN. // IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT // NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. #ifndef _CRB_TimSlotH_ #define _CRB_TimSlotH_ #include "crb_connectors.h" #include "monopins.h" // All necessary decoupling capacitors are already included. // CB_Rod_Tim: Interface between ROD and TIM class CB_Rod_Tim : public TBundle { public: port TCLK_N; // clock output from TIM port TCLK_P; port BUSY_N; // busy output from ROD port TTC; // TTC parallel output from TIM virtual void Register() { reg( TCLK_N ); reg( TCLK_P ); reg( BUSY_N ); regb( TTC, 7, 0 ); } }; // CB_Rod_Tim: Interface between Terminators and TIM class CB_Term_Tim : public TBundle { public: port TTC_L; // terminated busses port TTC_R; virtual void Register() { regb( TTC_L, 7, 0 ); regb( TTC_R, 7, 0 ); } }; // CM_TimSlot: TTC Interface Module (TIM) slot class CM_TimSlot : public TModule { // Tim Slot Subsystem public: // ***** member bundles ***** // CB_Rod_Tim Rod[ 22 ]; // only 5-12 and 14-21 will be registered -- others will be ignored CB_Term_Tim Term; // ***** member ports ***** // port VCC5; // 5V port VCC3; // 3.3V port GND; // L refers to slots on the left of the TIM: 5-12 // R refers to slots on the right of the TIM: 14-21 // ***** member modules and parts ***** // CP_CRB_TIMJ3 J3; CP_MONOPIN60 TIM_BUSY_OUT_TP; // decoupling enum { v3_cdc_count = 2, // >>> place one at each end of slot v5_cdc_count = 2 }; // >>> place one at each end of slot CP_CDC_POS V3_CDC[ v3_cdc_count ]; // ceramic decoupling for backplane 3.3V CP_CDC_POS V5_CDC[ v5_cdc_count ]; // ceramic decoupling for backplane 5.0V virtual void Register() { // bundles for ( int i = 5; i <= 21; ++ i ) { // for each slot if ( i == 13 ) continue; // TIM is in slot 13 regn( Rod, i ); // register the ROD interface } reg( Term ); // ports reg( VCC5 ); reg( VCC3 ); reg( GND ); // parts and modules reg( J3 ); reg( TIM_BUSY_OUT_TP ); rega( V3_CDC, v3_cdc_count ); rega( V5_CDC, v5_cdc_count ); } virtual void Connect() { wireall( GND ); wireall( VCC3, "VPOS3_3" ); wireall( VCC5, "VPOS5" ); for ( int i = 0; i < v3_cdc_count; ++ i ) VCC3 << V3_CDC[ i ].POS; for ( int i = 0; i < v5_cdc_count; ++ i ) VCC5 << V5_CDC[ i ].POS; GND << J3.ROD_SENSE; // ROD_SENSE must be grounded for TIM to enable its outputs // <<< route all TCLK_N/TCLK_P pairs as differential pairs // <<< TCLK_N/TCLK_P pairs must have differential impedance == 110 ohm (55 ohm line impedance) // <<< impedance for TTC bus must be in the range of 75 ohm to 100 ohm (~100 ohm preferred) // clock looped back to TIM "TIM_TCLK_N" << J3.TIM_TCLK_OUT_N << J3.TIM_TCLK_IN_N; // <<< match length to standard clock trace length "TIM_TCLK_P" << J3.TIM_TCLK_OUT_P << J3.TIM_TCLK_IN_P; // <<< match length to standard clock trace length "TIM_BUSY_OUT" << TIM_BUSY_OUT_TP.A << J3.TIM_BUSY_OUT; // <<< place TIM_BUSY_OUT_TP where it is accessible // These loops determine the mapping of TIM TCLK outputs to ROD slots. The mapping is chosen to facilitate matching TCLK trace lengths // BUSY signals are mapped 5->5, 6->6, ... 21->21 regardless of TCLK mapping // The ROD TCLK inputs are at J6 rows 24 and 25, i.e., at the bottom of the crate. // TIM clock outputs are located as follows: // // 5 6 ... 11 12 TIM13 14 15 ... 20 21 // --- 5 14 -- // | 6 15 | // | ... ... | // v 11 20 v // <----------------- 12 21 -----------------> ROD TCLK inputs are down here // --> the left side should be mapped 5->12, 6->11, ... // --> the right side should be mapped 14->14, 15->15, ... for ( int i = 5; i <= 12; ++ i ) { // for each slot to the left of the TIM Rod[ i ].TCLK_N << J3.TCLK_L_N( 17-i ); // <<< match length to standard clock trace length Rod[ i ].TCLK_P << J3.TCLK_L_P( 17-i ); // <<< match length to standard clock trace length Rod[ i ].BUSY_N << J3.BUSY_L_N( i ); // BUSY's are mapped 5->5, 6->6, ... for all slots Rod[ i ].TTC << J3.TTC_L; } for ( int i = 14; i <= 21; ++ i ) { // for each slot to the right of the TIM Rod[ i ].TCLK_N << J3.TCLK_R_N( i ); // <<< match length to standard clock trace length Rod[ i ].TCLK_P << J3.TCLK_R_P( i ); // <<< match length to standard clock trace length Rod[ i ].BUSY_N << J3.BUSY_R_N( i ); Rod[ i ].TTC << J3.TTC_R; } Term.TTC_L << J3.TTC_L; // terminators Term.TTC_R << J3.TTC_R; // the remainder of this function wires up no-connects "/NC" << J3.NC; "/NC" << J3.TIM_OK; // <<< bus this to ROD's (driven by TIM)? "/NC" << J3.LASER_ILOCK; // <<< bus this to ROD's (OC drive from ROD's)? "/NC" << J3.BOC_LAS_EN; // <<< bus this to TM's? drive with opto isolator? fiber input? } }; #endif
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