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C++BOLD Example Design: CRB

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _CRB_RodSlotH_
#define _CRB_RodSlotH_
 
#include "crb_connectors.h"
#include "crb_tim_slot.h"     // for ROD/TIM interface
 
// All necessary decoupling capacitors are already included.
 
// CM_RodSlot: ReadOut Driver slot
 
class CM_RodSlot : public TModule {      // Rod Slot Subsystem
public:
 
// ***** member bundles ***** //
  CB_Rod_Tim  Tim;   // interface to TIM
 
// ***** member ports ***** //
  port VCC5;     // 5V
  port VCC3;     // 3.3V
  port GND;
 
 
// ***** member modules and parts ***** //
  CP_CRB_J5P5   J5;
  CP_CRB_J6P6   J6;
 
 
 
  // decoupling
  enum {
         v3_cdc_count =  2,       // >>> place one at each end of slot
         v5_cdc_count =  2 };     // >>> place one at each end of slot
  CP_CDC_POS  V3_CDC[ v3_cdc_count ];    // ceramic decoupling for backplane 3.3V
  CP_CDC_POS  V5_CDC[ v5_cdc_count ];    // ceramic decoupling for backplane 5.0V
 
 
  virtual void Register() {
 
// bundles
    reg(  Tim    );
 
// ports
    reg(  VCC5   );
    reg(  VCC3   );
    reg(  GND    );
 
 
// parts and modules
 
    reg( J5 );
//    J5.SetPackage( "CONN_2MM_6X22_INV" );   // use footprint with inverted row numbers
 
    reg( J6 );
//    J6.SetPackage( "CONN_2MM_6X25_INV" );   // use footprint with inverted row numbers
 
    rega( V3_CDC, v3_cdc_count );
    rega( V5_CDC, v5_cdc_count );
  }
 
  virtual void Connect() {

    wireall( GND );
    wireall( VCC3, "VPOS3_3" );
    wireall( VCC5, "VPOS5" );
 
    for ( int i = 0; i < v3_cdc_count; ++ i )  VCC3  <<  V3_CDC[ i ].POS;
    for ( int i = 0; i < v5_cdc_count; ++ i )  VCC5  <<  V5_CDC[ i ].POS;
 
 
    Tim.TCLK_P  <<  J6.TCLKIP;      // these are inputs to the ROD and TM
    Tim.TCLK_N  <<  J6.TCLKIN;
    Tim.TTC     <<  J6.TG( 7, 0 );  // these are inputs to the ROD and TM (but not used on the TM)
 
    Tim.BUSY_N  <<  J5.BUSY_N;      // this is an output to the TIM
 
// the remainder of this function wires up no-connects
// most no-connects are signals passed between the ROD and TM with no connection on the backplane
 
    "/NC"  <<  J5.RCLKIP;   // inputs to ROD
    "/NC"  <<  J5.RCLKIN;
 
    "/NC"  <<  J5.RCLKOP;   // outputs from ROD
    "/NC"  <<  J5.RCLKON;
 
    "/NC"  <<  J5.SCLKOP;
    "/NC"  <<  J5.SCLKON;
 
    "/NC"  <<  J5.TCLKOP;
    "/NC"  <<  J5.TCLKON;

    merge( "/NC", J5.BG_B1(  7, 0 ) );
    merge( "/NC", J5.BG_A1( 15, 0 ) );
    merge( "/NC", J5.BG_B2( 15, 0 ) );
    merge( "/NC", J5.BG_A2( 15, 0 ) );
    merge( "/NC", J5.BG_B3( 15, 0 ) );
 
    merge( "/NC", J6.BG_A3( 15, 0 ) );
    merge( "/NC", J6.BG_B4( 15, 0 ) );
    merge( "/NC", J6.BG_A4( 15, 0 ) );
    merge( "/NC", J6.BG_B5( 15, 0 ) );
    merge( "/NC", J6.BG_A5( 15, 0 ) );
 
    merge( "/NC", J6.TG( 15, 8 ) );  // TG( 7, 0 ) are used for bussed TTC() connections, but these are pass-thru
 
  }
};
 
#endif