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C++BOLD Example Design: IROD

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _DXB_FPGAH_
#define _DXB_FPGAH_
 
#include "std_fpga.h"
 
// Data Exchange Back End FPGA
 
class CM_DXB_FPGA : public TModule {
public:
// ***** member bundles ***** //
  CB_JTAG_CONF JTAG_CONF;
 
// ***** member ports ***** //
  port VCC;          // 3.3V
  port VB;           // 2.5V for FPGA internal
  port GND;
                     // Host asynchronous EMIF connections
  port D;            // data (32 bits)
  port A;            // address (4 bits)
  port STB_N;        // one strobe per FPGA
  port WR_N;         // one read/write* signal to all FPGA's
 
  port DCLK;         // DX output clock, currently used only by DXB FPGA
  port DX_CLK;       // DX Clock (front end), ~40 MHz
  port DXINT_CLK;    // DX Internal Clock (back end), ~70MHz
 
  port INTER_DX;     // Signals between DXF', DXB, and FIFO (34 wires), typical use:
                     //   0-31 data                       bussed between all DX FPGA's and FIFO
                     //     32 control bit                bussed, with pullup for OR-tie
                     //     33 spare                      bussed, with pullup for OR-tie
 
  port INTER_DX_A;   // bits 34 and 35 of INTER_DX are routed pt-to-pt to the DXF FPGA's, typical use:
  port INTER_DX_B;   //     34 almost full from DXB FIFO  one wire per DXF FIFO
                     //     35 write enable to DXB FIFO   one wire per DXF FIFO
 
  port DXB_HG;       // generic connections to HPU (4 wires), uses TBD:
 
  port DG;           // generic connections to backplane (57 wires)
 
// ***** member modules and parts ***** //
  CM_STD_FPGA  Fpga;
 
  virtual void Register() {
// bundles
    reg(  JTAG_CONF );
 
// ports
    reg(   VCC );
    reg(   VB  );
    reg(   GND );
 
    regb(  D, 31, 0 );
    regb(  A,  3, 0 );
    reg(   STB_N );
    reg(   WR_N );
 
 
    reg(  DCLK );
    reg(  DX_CLK );
    reg(  DXINT_CLK );
 
    regb( INTER_DX,   33,  0 );
    regb( INTER_DX_A, 35, 34 );
    regb( INTER_DX_B, 35, 34 );
 
    regb( DXB_HG, 3, 0 );
 
    regb( DG, 56, 0 );
 
 
// parts and modules
    reg( Fpga );
  }
 
  virtual void Connect() {
 
    wire( VCC );
    wire( VB  );
    wire( GND );
 
    JTAG_CONF << Fpga.JTAG_CONF;
 
 // bus between all DX FPGA's
    INTER_DX(   17,  0 ) << Fpga.Bank[ 6 ](  0, 17 );   //  18 note inverted range  -->  0 remaining in bank 6
    INTER_DX(   33, 18 ) << Fpga.Bank[ 7 ](  2, 17 );   // +16 note inverted range  -->  2 remaining in bank 7
 
    INTER_DX_A( 35, 34 ) << Fpga.Bank[ 7 ](  0,  1 );   // + 2 note inverted range  -->  0 remaining in bank 7
    INTER_DX_B( 35, 34 ) << Fpga.Bank[ 0 ]( 14, 15 );   //   2 note inverted range  --> 14 remaining in bank 0
 
    DG( 16,  0 ) << Fpga.Bank[ 3 ];            //  17  -->  0 remaining in bank 3
    DG( 33, 17 ) << Fpga.Bank[ 2 ];            // +17  -->  0 remaining in bank 2
    DG( 50, 34 ) << Fpga.Bank[ 1 ]( 16, 0 );   // +17  -->  1 remaining in bank 1 (used below for STB_N)
    DG( 56, 51 ) << Fpga.Bank[ 0 ](  5, 0 );   // + 6  -->  8 remaining in bank 0
 
  // connections to Host EMIF
    D( 17,  0 )    <<  Fpga.Bank[ 4 ]( 0, 17 );   //  18 note inverted range  --> 0 remaining in bank 4
    D( 31, 18 )    <<  Fpga.Bank[ 5 ]( 1, 14 );   // +14 note inverted range  --> 1 remaining in bank 5
 
    A              <<  Fpga.Bank[ 0 ]( 9, 6  );   //   4  -->  4 remaining in bank 0
 
        // connect STB_N to global clock and adjacent user I/O pin
        // reduce complaining by the logic synthesizer when STB_N is factored into IOB OE (?)
    STB_N          <<  Fpga.Bank[ 1 ]( 17 )       //   1  -->  0 remaining in bank 1
                   <<  Fpga.GCK( 2 );
 
    WR_N           <<  Fpga.Bank[ 5 ]( 0 );       //   1  -->  0 remaining in bank 5
 
    DXB_HG         <<  Fpga.Bank[ 0 ]( 13, 10 );  //   4  -->  0 remaining in bank 0
 
 
// clocks (see also STB_N, above)
    DCLK           <<  Fpga.GCK( 0 );
    DX_CLK         <<  Fpga.GCK( 1 );
    DXINT_CLK      <<  Fpga.GCK( 3 );
 
  }
};
 
#endif