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C++BOLD Example Design: IROD

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _DXF_FPGAH_
#define _DXF_FPGAH_
 
#include "std_fpga.h"
 
// Data Exchange Front End FPGA
 
class CM_DXF_FPGA : public TModule {
public:
// ***** member bundles ***** //
  CB_JTAG_CONF JTAG_CONF;
 
// ***** member ports ***** //
  port VCC;          // 3.3V
  port VB;           // 2.5V for FPGA internal
  port GND;
                     // Host asynchronous EMIF connections
  port D;            // data (32 bits)
  port A;            // address (4 bits)
  port STB_N;        // one strobe per FPGA
  port WR_N;         // one read/write* signal to all FPGA's
 
  port DCLK;         // DX output clock, currently used only by DXB FPGA
  port DX_CLK;       // DX Clock (front end), ~40 MHz
  port DXINT_CLK;    // DX Internal Clock (back end), ~70MHz
 
  port DXD;          // data bus to DPU's of half-ROD (32 wires)
  port DXC;          // control bus (4 MSB's have external pullups for OR-tie),e.g., used for DAV, END, AL_END, BROADCAST, DEST_AF
 
  port HF_MRS_N;           // Host Fifo master reset
  port HF_WEN_N;           // Host Fifo Write Enable
  port HF_LD_N;            // Host Fifo offset load (for loading programmable flag offset)
  port HF_PAF_N;           // Host Fifo almost full flag
  port STRAP;              // Strap telling which FPGA (A or B) this is
 
  port INTER_DXF;          // Signals between DXF A and DXF B (4 wires)
  port INTER_DX;           // Signals between DXF's, DXB and FIFO (36 wires), typical use:
                           //   0-31 data                       bussed between all DX FPGA's and FIFO
                           //     32 control bit                bussed, with pullup for OR-tie
                           //     33 spare                      bussed, with pullup for OR-tie
                           //     34 almost full from DXB FIFO  one wire per DXF FIFO
                           //     35 write enable to DXB FIFO   one wire per DXF FIFO
 
  port DXF_HG;             // generic connections to HPU (4 wires), typical use:
                           //      0 NOTIFY_FRONT    bussed to both DXF FPGA's, with pullup for OR-tie
                           //      1 NOTIFY_BACK     bussed to both DXF FPGA's, with pullup for OR-tie
                           //      2 INST_FIFO_AF    bussed to both DXF FPGA's, with pullup for OR-tie
                           //      3 spare           bussed to both DXF FPGA's, with pullup for OR-tie
 
 
 
// ***** member modules and parts ***** //
  CM_STD_FPGA  Fpga;
 
  virtual void Register() {
// bundles
    reg(  JTAG_CONF );
 
// ports
    reg(   VCC );
    reg(   VB  );
    reg(   GND );
 
    regb(  D, 31, 0 );
    regb(  A,  3, 0 );
    reg(   STB_N );
    reg(   WR_N );
 
 
    reg(  DCLK );
    reg(  DX_CLK );
    reg(  DXINT_CLK );
 
    regb( DXD, 31, 0 );
    regb( DXC,  9, 0 );
 
    reg(  HF_MRS_N );
    reg(  HF_WEN_N );
    reg(  HF_LD_N );
    reg(  HF_PAF_N );
    reg(  STRAP );
 
    regb( INTER_DXF,   3, 0 );
    regb( INTER_DX, 35, 0 );
    regb( DXF_HG, 3, 0 );
 
// parts and modules
//    Fpga.UseVref( 0, 7, 6 );  // formerly intended for DXD and DXC banks
    reg( Fpga );
  }
 
  virtual void Connect() {
 
    wire( VCC );
    wire( VB  );
    wire( GND );
 
    JTAG_CONF << Fpga.JTAG_CONF;
 
 // bus between all DX FPGA's
    INTER_DX( 16,  0 ) << Fpga.Bank[ 3 ];            //  17
    INTER_DX( 33, 17 ) << Fpga.Bank[ 2 ];            // +17
    INTER_DX( 35, 34 ) << Fpga.Bank[ 1 ]( 1 , 0 );   // + 2  --> 16 remaining in bank 1
 
 // bus to DPU's in half-ROD
    DXD( 17,  0 )  <<  Fpga.Bank[ 6 ](  0, 17 );   //  18 note inverted range  -->  0 remaining in bank 6
    DXD( 31, 18 )  <<  Fpga.Bank[ 7 ](  4, 17 );   // +14 note inverted range  -->  4 remaining in bank 7
 
    DXC(  3,  0 )  <<  Fpga.Bank[ 7 ](  0,  3 );   //   4 note inverted range  -->  0 remaining in bank 7
    DXC(  9,  4 )  <<  Fpga.Bank[ 0 ]( 10, 15 );   //  +6 note inverted range  --> 10 remaining in bank 0
 
 
// ID strap tells FPGA which DXF FPGA it is (possibly optional)
    STRAP          <<  Fpga.Bank[ 0 ]( 0 );       //   1  -->  9 remaining in bank 0
 
// miscellaneous Host FIFO connections
    HF_MRS_N       <<  Fpga.Bank[ 0 ]( 1 );       //   1  -->  8 remaining in bank 0
    HF_WEN_N       <<  Fpga.Bank[ 0 ]( 2 );       //   1  -->  7 remaining in bank 0
    HF_LD_N        <<  Fpga.Bank[ 0 ]( 3 );       //   1  -->  6 remaining in bank 0
    HF_PAF_N       <<  Fpga.Bank[ 0 ]( 4 );       //   1  -->  5 remaining in bank 0
 
  // connections to Host EMIF
    D( 17,  0 )    <<  Fpga.Bank[ 4 ]( 0, 17 );   //  18 note inverted range
    D( 31, 18 )    <<  Fpga.Bank[ 5 ]( 1, 14 );   // +14 note inverted range  --> 1 remaining in bank 5
 
    A              <<  Fpga.Bank[ 1 ]( 5, 2  );   //   4  --> 12 remaining in bank 1
 
        // connect STB_N to global clock and adjacent user I/O pin
        // reduce complaining by the logic synthesizer when STB_N is factored into IOB OE (?)
    STB_N          <<  Fpga.Bank[ 1 ]( 17 )       //   1  --> 11 remaining in bank 1
                   <<  Fpga.GCK( 2 );
 
    WR_N           <<  Fpga.Bank[ 1 ]( 16 );      //   1  --> 10 remaining in bank 1
 
 
    INTER_DXF      <<  Fpga.Bank[ 1 ](  9,  6 );  //   4  -->  6 remaining in bank 1
    DXF_HG         <<  Fpga.Bank[ 1 ]( 13, 10 );  //   4  -->  2 remaining in bank 1
 
 
    merge( "/NC",      Fpga.Bank[ 0 ](  9,  5 ) );
    merge( "/NC",      Fpga.Bank[ 1 ]( 15, 14 ) );
    merge( "/NC",      Fpga.Bank[ 5 ](      0 ) );
 
 
// clocks (see also STB_N, above)
    DCLK           <<  Fpga.GCK( 0 );
    DX_CLK         <<  Fpga.GCK( 1 );
    DXINT_CLK      <<  Fpga.GCK( 3 );
 
  }
};
 
#endif