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C++BOLD Reference Manual

2.4.4. Making Connections

The Connect() function records the connections within a module. Within the Connect() function, connections are typically made by using the << operator or one of the other CBOLD connection operators or functions. For example:

...
  virtual void Connect() {
    DATA << Ram.D        << Rom.D;        // connect    all bits of the    data bus   to this module's DATA port
    ADDR << Ram.A(11, 0) << Rom.A(11, 0); // connect     12 bits of the address bus   to this module's ADDR port
    merge( GND, Ram.A(15, 12) );          // connect unused bits of the address ports to this module's  GND port
    merge( GND, Rom.A(17, 12) );
  }
...

For details on the many ways to make connections, see Connections.

The example below is a complete module that shows typical code for Register() and Connect():

// Supervisor Circuit
// includes required decoupling and protection resistor
 
class CM_Supervisor5_3 : public TModule {
public:
  port VCC;       // sense2 voltage and supply voltage: 3.3V
  port VCC5;      // sense1 voltage, protected with 1k resistor: 5V
  port GND;
  port MR_N;      // manual reset in
  port WDI;       // watchdog in
  port RESET;     // reset outputs
  port RESET_N;
  CP_TPS3305_33D  Supr;      // supervisor chip
  CP_R1K          Rsense1;   // resistor to protect SENSE1 input of supervisor
  CP_CDC_POS      CDC;       // decoupling capacitor required for supervisor stability
 
public:
  virtual void Register() {
    reg( VCC );              // register all ports
    reg( VCC5 );
    reg( GND );
    reg( MR_N );
    reg( WDI );
    reg( RESET );
    reg( RESET_N );
    reg( Supr );             // register all parts
    reg( Rsense1 );
    reg( CDC );
  }
 
  virtual void Connect() {
    VCC << Supr.VCC << Supr.SENSE2 << CDC.POS;
    GND << Supr.GND                << CDC.GND;
    VCC5 ^ Rsense1 ^ "SENSE1" << Supr.SENSE1;  // protect SENSE1 with series resistor as per data sheet
    wire( MR_N );                              // connect module ports to part ports having the same name
    wire( WDI );                               // e.g., this connects this module's port WDI to Supr.WDI
    wire( RESET );
    wire( RESET_N );
  }
};

Unlike most schematic capture tools, CBOLD does not require the designer to specify port types (e.g., IN, OUT, POWER, etc.) or direction (e.g., IN, OUT, INOUT).

CBOLD reports potential connectivity mistakes, e.g., unconnected pins not in the global no–connect net. It also enforces connectivity rules, e.g., by causing runtime errors when the designer attempts to connect port ranges having different widths.

CBOLD does not perform electrical rules checking. See Why does CBOLD Lack an Electrical Rules Checker?