Coolquest, Inc.	Home	Products	Support	About	Contact
C++BOLD Example Design: IROD

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _TTC_FPGAH_
#define _TTC_FPGAH_
 
#include "std_fpga.h"
#include "dallas.h"  // for temp sensors
 
class CM_TTC_FPGA : public TModule {    // TTC FPGA for Interconnect Subsystem
public:
// ***** member bundles ***** //
  CB_JTAG_CONF   JTAG_CONF;
 
// ***** member ports ***** //
  port VCC;     // 3.3V
  port VB;      // 2.5V for FPGA internal
  port GND;
 
  port RCLK;       // clocks
  port SCLK;
  port TCLK;
                   // Host asynchronous EMIF connections
  port D;          // data
  port A;          // address
  port STB_N;      // one strobe per FPGA
  port WR_N;       // one read/write* signal to all FPGA's
 
  port BUS_A;      // bussed connections to DPU's, one bus per HalfROD
  port BUS_B;
 
  port BPI[ 6 ];   // generic connections to the BPI FPGA's
  port CEN[ 2 ];   // additional connections to the two central BPI FPGA's
 
  port HG;         // generic HPU connections
 
                   // generic backplane connections
  port TG;         // A and B are suggestions for optimal FPGA internal routing
 
  port FP_TTC;     // front panel general-purpose inputs to TTC FPGA
 
  port TMP_N;      // transition module present indicator
 
 
// ***** member modules and parts ***** //
  CM_STD_FPGA  Fpga;
  CP_DS1775R  TempSensor[ 3 ];   // these are here mostly because spare pins are available on the TTC FPGA
  CP_R10K     PullupTemp[ 3 ];   // pullups for temp sensors
 
  virtual void Register() {
// bundles
    reg( JTAG_CONF );
 
// ports
    reg(   VCC );
    reg(   VB  );
    reg(   GND );
 
    reg(   RCLK );
    reg(   SCLK );
    reg(   TCLK );
 
    regb(  D, 15, 0 );
    regb(  A,  3, 0 );
    reg(   STB_N );
    reg(   WR_N );
 
    regb(  BUS_A, 5, 0 );
    regb(  BUS_B, 5, 0 );
 
    regab( BPI,   6, 7, 0 );    // array of six 8-bit busses
    regab( CEN,   2, 3, 0 );    // four additional connections to each of the central BPI FPGA's
    regb(  HG,    7, 0 );
    regb(  TG,   15, 0 );
 
    regb(  FP_TTC, 1, 0 );
 
    reg(   TMP_N );
 
// parts and modules
    Fpga.UseVref( 3, 4 );    // use VREF on banks 3, 4 --> better noise margin for TG
    reg( Fpga );
    rega( TempSensor, 3 );
    rega( PullupTemp, 3 );
  }
 
  virtual void Connect() {
 
    wireall( VCC );
    wire(    VB  );
    wireall( GND );
 
    JTAG_CONF << Fpga.JTAG_CONF;
 
  // connections to Host EMIF
    A         <<  Fpga.Bank[ 0 ]( 15, 12 );
    D         <<  Fpga.Bank[ 7 ]( 15,  0 );
    WR_N      <<  Fpga.Bank[ 1 ]( 16 );
 
 
  // generic connections to the BPI FPGA's
    BPI[ 0 ]  <<  Fpga.Bank[ 2 ](  7, 0 );
    BPI[ 1 ]  <<  Fpga.Bank[ 1 ](  7, 0 );
    CEN[ 0 ]  <<  Fpga.Bank[ 1 ]( 11, 8 );   // BPI FPGA 1 is a central FPGA --> four more connections to TTC FPGA
    BPI[ 2 ]  <<  Fpga.Bank[ 0 ](  7, 0 );
    BPI[ 3 ]  <<  Fpga.Bank[ 6 ](  7, 0 );
    BPI[ 4 ]  <<  Fpga.Bank[ 5 ](  7, 0 );
    CEN[ 1 ]  <<  Fpga.Bank[ 5 ]( 11, 8 );   // BPI FPGA 4 is a central FPGA --> four more connections to TTC FPGA
    BPI[ 5 ]  <<  Fpga.Bank[ 4 ](  7, 0 );
 
  // generic connections to Host
    HG  <<  Fpga.Bank[ 6 ]( 15, 8 );
 
  // generic backplane connections
    TG(  1,  0 ) << Fpga.Bank[ 4 ]( 14, 13 );
    TG( 15,  2 ) << Fpga.Bank[ 3 ];
 
  // general-purpose front-panel inputs
    FP_TTC( 0 )  << Fpga.Bank[ 7 ]( 16 );
    FP_TTC( 1 )  << Fpga.Bank[ 7 ]( 17 );
 
  // temperature sensors
    "TEMP_SDAT"  << Fpga.Bank[ 0 ]( 10,  8 );  // for readable net name
    "TEMP_SCLK"  << Fpga.Bank[ 0 ]( 11 );
 
    for ( int i = 0; i < 3; ++ i ) {
      Fpga.Bank[ 0 ]( 8 + i )  << TempSensor[ i ].SDA  ^ PullupTemp[ i ] ^ VCC;  // individual serial data with pullup
      "TEMP_SCLK"              << TempSensor[ i ].SCL;                           // serial clock to all sensors
      "/NC"                    << TempSensor[ i ].OS;                       // thermostat output signal
    }
 
    TMP_N      <<  Fpga.Bank[ 2 ]( 16 );   // transition module present indicator, pulled high in CM_Interconnect, grounded on TM
 
  // clocks
    STB_N          <<  Fpga.Bank[ 1 ]( 17 )       // >>> this pin is adjacent to GCK2
                   <<  Fpga.GCK( 2 );
 
    TCLK           <<  Fpga.GCK( 0 );
    SCLK           <<  Fpga.GCK( 1 );
    RCLK           <<  Fpga.GCK( 3 );
 
  // generic busses to HalfROD's
    BUS_B( 5, 2 )  <<  Fpga.Bank[ 1 ](  15, 12 );  // 0 remaining in bank 1
    BUS_B( 1, 0 )  <<  Fpga.Bank[ 2 ](  15, 14 );
    BUS_A          <<  Fpga.Bank[ 2 ](  13,  8 );  // 0 remaining in bank 2
 
    merge( "/NC",  Fpga.Bank[ 4 ]( 12,  8 ) );   // 5 unused  (VREF-referenced I/O available)
    merge( "/NC",  Fpga.Bank[ 5 ]( 14, 12 ) );   // 3 unused
    merge( "/NC",  Fpga.Bank[ 6 ]( 17, 16 ) );   // 2 unused
 
  }
};
 
#endif