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C++BOLD Example Design: IROD

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _BPI_FPGAH_
#define _BPI_FPGAH_
 
#include "std_fpga.h"
 
class CM_BPI_FPGA : public TModule {    // BPI FPGA for Interconnect Subsystem
public:
// ***** member bundles ***** //
  CB_JTAG_CONF JTAG_CONF;
 
// ***** member ports ***** //
  port VCC;     // 3.3V
  port VB;      // 2.5V for FPGA internal
  port GND;
 
  port RCLK;       // clocks
  port SCLK;
  port TCLK;
 
                   // Host asynchronous EMIF connections
  port D;          // data
  port A;          // address
  port STB_N;      // one strobe per FPGA
  port WR_N;       // one read/write* signal to all FPGA's
 
  port DPU_A;      // generic DPU connections
  port DPU_B;
 
  port BG_A;       // A and B are suggestions for optimal FPGA internal routing
  port BG_B;
 
  port AUX;        // pins used for several purposes:
                   //   TTC (all FPGA's)
                   //   more TTC (central FPGA's only)
                   //   connections to BG's of central BPI FPGA's (all except central FPGA's)
                   //   connections to non-central FPGA's of other side (central FPGA's only)
  port CROSS;      // cross connections between sides
                   // generic backplane connections
 
// ***** member modules and parts ***** //
  CM_STD_FPGA  Fpga;
  virtual void Register() {
// bundles
    reg( JTAG_CONF );
 
// ports
    reg(   VCC );
    reg(   VB  );
    reg(   GND );
 
    reg( RCLK );
    reg( SCLK );
    reg( TCLK );
 
    regb(     D,  3, 0 );
    regb(     A,  3, 0 );
    reg(  STB_N );
    reg(   WR_N );
 
    regb( DPU_A, 24, 0 );
    regb( DPU_B, 24, 0 );
 
    regb( BG_A, 15, 0  );
    regb( BG_B, 15, 0  );
 
    regb( AUX,   23, 0 );
    regb( CROSS,  5, 0 );
 
// parts and modules
    Fpga.UseVref( 1, 2, 3, 4 );    // use VREF on banks 1, 2, 3, 4 --> better noise margin for BG's and AUX's
    reg( Fpga );
  }
 
  virtual void Connect() {
 
    wire( VCC );
    wire( VB  );
    wire( GND );
 
    JTAG_CONF << Fpga.JTAG_CONF;
 
// DPU's should be approximately opposite corresponding BG's
    DPU_A( 24,  7 )  <<  Fpga.Bank[ 6 ]( 0, 17 );   // note inverted range
    DPU_A(  6,  0 )  <<  Fpga.Bank[ 5 ]( 0,  6 );   // note inverted range
 
    DPU_B( 17,  0 )  <<  Fpga.Bank[ 7 ]( 0, 17 );   // note inverted range
    DPU_B( 24, 18 )  <<  Fpga.Bank[ 0 ]( 9, 15 );   // note inverted range
 
// generic connections to backplane
    BG_A( 13,  0 )  <<  Fpga.Bank[ 3 ];              //  14 (all of bank 3)
    BG_A( 15, 14 )  <<  Fpga.Bank[ 2 ](  1, 0 );     // + 2 more
    BG_B( 11,  0 )  <<  Fpga.Bank[ 2 ]( 13, 2 );     //  12 (remainder of bank 2)
    BG_B( 15, 12 )  <<  Fpga.Bank[ 1 ](  3, 0 );     // + 4 more
 
    AUX(  23, 15 )  <<  Fpga.Bank[ 1 ]( 12, 4 );     //   9
    AUX(  14,  0 )  <<  Fpga.Bank[ 4 ];              // +15 (all of bank 4 )
 
// connections to central FPGA on other side of Interconnect subsystem
    CROSS           <<  Fpga.Bank[ 5 ]( 12, 7 );     //   6
 
// connections to Host EMIF
    A               <<  Fpga.Bank[ 0 ](  3,  0 );
    D               <<  Fpga.Bank[ 0 ](  7,  4 );
 
    WR_N            <<  Fpga.Bank[ 1 ]( 13 );
    STB_N           <<  Fpga.Bank[ 1 ]( 14 )       // this pin is adjacent to GCK2
                    <<  Fpga.GCK( 2 );
 
    TCLK            <<  Fpga.GCK( 0 );
    SCLK            <<  Fpga.GCK( 1 );
    RCLK            <<  Fpga.GCK( 3 );
 
 
    merge( "/NC",       Fpga.Bank[ 0 ](      8 ) );
    merge( "/NC",       Fpga.Bank[ 5 ]( 14, 13 ) );
  }
};
 
#endif