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C++BOLD Reference Manual

7.2.9. Bundles and the wire() Function

The previously described forms of wire() and wireall() ignore bundles.

The CBOLD framework provides a form of wire() designed specifically to connect ports of a module, part or bundle to identically named (and ranged) ports of a bundle:

wire( Jtag,  MyFPGA      );    // connect FPGA's TMS, TCK, TDI, and TDO ports to the corresponding ports of the Jtag bundle
wire( Slink, MyConnector );    // connect matching ports of MyConnector to Slink bundle

The examples above illustrate the same typical use of this form of wire(): connecting individual pins of a part to a bundle.

The first example connects an FPGA's individual JTAG pins to a bundle that encapsulates the JTAG interface, e.g.:

class CB_JTAG : public TBundle {  // JTAG bundle
public:
  port TMS;
  port TDI;
  port TDO;
  port TCK;
  ...
};

In the second example, MyConnector would have ports appropriately named to match ports in the Slink bundle.

There is only one form of wire() that accepts bundles as arguments. The first argument is a bundle and the second argument is a module, part or bundle. Both arguments are required.

A runtime error results if wire() found no member ports of the second argument that match a member port of the first argument. A match requires both the port name and range (e.g., (31,0)) to be identical. Both left (e.g., 31) and right (e.g, 0) extents of the range must match. A width match alone is insufficient.

This form of wire() descends all bundles recursively, whether they are encountered as members of the first argument or the second argument. I.e., the function considers a port to be a member of one of the arguments if its ultimate owner is the argument.