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C++BOLD Reference Manual

7.6. Netlist Extraction

Under Construction

Net names assigned by the user at a higher level of the hierarchy will override those assigned at a lower level.

Net names assigned by the user will always override automatically assigned net names, regardless of the hierarchy levels where the assignments are made.

In general, the designer should attempt to assign a meaningful name to every net. It is legal to do otherwise.

Nonetheless, the designer should assign net names only as needed, because superfluous user-assigned net names can cause confusion and clutter a design.

The general rule is to assign net names as high in the hierarchy as possible. This implies that the user should avoid assigning names to connections between a module's ports and the ports of its members. For example:

class TMyFpgaWrapper: TModule {
public:
  port VCC;
  port GND;
  port DXP;     // anode    of FPGA's temp-sensing diode
  port DXN;     // cathode
  ...
  CP_R4_7K   DONE_Pullup;
  ...
  virtual void Connect() {
    VCC ^ DONE_Pullup ^ "DONE" << Fpga.DONE;   // assign name DONE, because DONE is internal to this module
    DXP << Fpga.DXP;                           // do not assign names to remaining connections
    DXN << Fpga.DXP;                           // -- they will be further connected in a higher-level module
    wireall( GND );
    ...
  }
};