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C++BOLD Reference Manual

20. Annotated Examples

20.1. CRB CM_Root - Example of Registering

The CRB is a custom passive backplane for a data acquisition system. It is designed to install in the P5/P6 area of a 21-slot 9U VME subrack. As noted in comments in the source code, the backplane is keyed to accept two types of 9U boards: a Timing Interface Module (TIM) and sixteen ReadOut Drivers (ROD's). The TIM slot is centered between two sets of eight ROD slots. The backplane does not include connectors for the leftmost four slots (slots 1-4), because these slots are reserved for 6U boards.

The example illustrates the following:

The registering code in the CRB example results in module names and reference designators that reflect the associated slot number. For example, the ROD's are in slots 5-12 and 14-21, and final RodSlot instance names are RodSlot5-RodSlot12 and RodSlot14-RodSlot21. The associated reference designators begin with R05-R12 and R14-R21. Likewise, the TIM is in slot 13, the TimSlot's instance name is TimSlot13, and its associated reference designators begin with T13.

The RodSlot array is declared with 22 elements (0-21), even though only 16 of these will be registered. (*1*)

An ostringstream is used as a convenient means of building the Reference base for the RodSlot's. (*2*) The following members and manipulators of ostringstream are used:

A single for loop in Register() cycles through all of the slots supported by the backplane. (*3*)

Slot 13 is a special case, because it is the slot keyed for the TIM rather than a ROD. (*4*)

Instead of using one of the registering macros (reg, regn, rega, regb, regab), Reg() is called directly. (*5*) This allows full flexibility in specifying:

The remaining members are registered normally. (*6*)

From Crb.h:

// Slot assignments:
//    Slot
//     1-3    no connector, slots are reserved for 6U boards
//       4    no connector, slot   is reserved for 6U/9U separator
//    5-12    R0-R7  (ROD's)
//      13    TIM
//   14-21    R8-R15 (ROD's)
 
class CM_Root : public TModule {
public:
// root–level module has no ports
 
// instantiate subsystems
  CM_RodSlot          RodSlot[ 22 ]; // only 16 of these are registered (5-12, 14-21) (*1*)
                                     // non-registered RodSlot's are ignored
  CM_TimSlot          TimSlot;
  CM_Terminators      Terminators;
  CM_Power            Power;
 
  virtual void Register() {
    ostringstream  RefBase;                   // (*2*)
 
    for ( int i =  5; i <= 21; ++ i ) {       // for each slot (*3*)
      if ( i == 13 ) {                        // TIM is in slot 13 (*4*)
        Reg( &TimSlot, "TimSlot", i );        // register TimSlot as TimSlot13 (*5*)
        TimSlot.SetReferenceBase( "T13" );    // use T13 as the base for all of its reference designators
        continue;
      }
      Reg( &RodSlot[ i ], "RodSlot", i );                                      // register the RodSlot (*5*)
      RefBase.str( "" );  RefBase << "R" << setw( 2 ) << setfill( '0' ) << i;  // set its ReferenceBase (*2*)
      RodSlot[ i ].CopyReferenceBase( RefBase.str().c_str() );
    }
    reg(  Terminators     );  Terminators.SetReferenceBase(     "TM" );        // (*6*)
    reg(  Power           );  Power.SetReferenceBase(           "PW" );
  }
 
  virtual void Connect() {
    ...
  }
};

20.2. IROD CM_Root and CM_HalfROD - Example of Hierarchical Reference Base

The IROD design is a large, complex multiprocessing motherboard. Its several subsystems are listed in the code excerpt below. Each of the IROD's two HalfROD subsystems contains an array of six Data Processing Units or DPU's.

The registration code in CM_Root and CM_HalfROD is designed to result in the following reference bases for the DPU's:

From Irod.h:

//  ************  IROD  ************
//  subsystem           abbreviation
//  ---------           ------------
//  Backplane           BK or Back (BP within the Clock Generation subsytem)
//  ClockGeneration     CG
//  DataExchange        DX
//  DPU_Control         DC
//  FrontPanel          FP or Front
//  HalfROD             Half
//    Half A            A
//    Half B            B
//  Host                HO or Host
//  Interconnect        IC
//  JTAG                JT or JTAG
//  Power               PW or PWR
//  VME_Interface       VM or VME
 
class CM_Root : public TModule {
public:
// root–level module has no ports
 
// instantiate subsystems
  CM_Backplane        Backplane;
  CM_ClockGeneration  ClockGeneration;
  CM_DataExchange     DataExchange;
  CM_DPU_Control      DPU_Control;
  CM_FrontPanel       FrontPanel;
  CM_HalfROD          Half_A;
  CM_HalfROD          Half_B;
  CM_Host             Host;
  CM_Interconnect     Interconnect;
  CM_JTAG             JTAG;
  CM_Power            Power;
  CM_VME_Interface    VME_Interface;
 
  virtual void Register() {
      //    subsystem                                     reference base
      // ---------------                                        --
    reg( Backplane       );  Backplane.SetReferenceBase(       "BK" );
    reg( ClockGeneration );  ClockGeneration.SetReferenceBase( "CG" );
    reg( DataExchange    );  DataExchange.SetReferenceBase(    "DX" );
    reg( DPU_Control     );  DPU_Control.SetReferenceBase(     "DC" );
    reg( FrontPanel      );  FrontPanel.SetReferenceBase(      "FP" );
    reg( Half_A          );  Half_A.SetReferenceBase(          "A"  );  // see CM_HalfROD for more ReferenceBase's
    reg( Half_B          );  Half_B.SetReferenceBase(          "B"  );
    reg( Host            );  Host.SetReferenceBase(            "HO" );
    reg( Interconnect    );  Interconnect.SetReferenceBase(    "IC" );
    reg( JTAG            );  JTAG.SetReferenceBase(            "JT" );
    reg( Power           );  Power.SetReferenceBase(           "PW" );
    reg( VME_Interface   );  VME_Interface.SetReferenceBase(   "VM" );
  }
 
  virtual void Connect() {
    ...
  }
};

From HalfROD.h:

class CM_HalfROD : public TModule {    // six DPU's
public:
  ...
  CM_DPU  DPU[ DPU_HalfCount ];        // array of six DPU modules (DPU_HalfCount is 6)
  ...
 
  virtual void Register() {
    ...
    rega( DPU, DPU_HalfCount );                                    // register the array of DPU's
    for ( int i = 0; i < DPU_HalfCount; ++ i ) {                   // assign separate reference base to each DPU
      char TempChar[ 64 ];                                         // itoa requires at most 33 chars
      char* cp = CharBucket.AddString( itoa( i, TempChar, 10 ) );  // pointer to permanent null-terminated char array
      DPU[ i ].SetReferenceBase( cp );
    }
    ...
  }
 
  virtual void Connect() {
    ...
  }
};

The final reference bases for the DPU's are hierarchical: A0-A5, B0-B5.