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C++BOLD Example Design: TTM

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _TtmH_
#define _TtmH_
 
#include "cb_base.h"
#include "cb_shorthand.h"
 
// above:  standard code
// below:  design-specific code
 
// Search all files for ">>>" to find important comments.
 
// file paths, etc
#define  DESIGN_NAME  "ttm"                                                                 // name of design--used primarily to form file names
//                    dir for all CBOLD output  subdir. for this design   base of file name
#define  OUTPUT_BASE  OUTPUT_PATH DIR_SEP       DESIGN_NAME DIR_SEP       DESIGN_NAME        // concatenation of path and name --> base for output file names
 
 
// files needed by many of the subsystems
#include "ttm_clones.h"     // cloned resisters, capacitors, etc.
#include "decoupling.h"
 
// subsystems
#include "ttm_asmlink.h"
#include "ttm_backplane.h"
#include "ttm_clocking.h"
#include "ttm_power.h"

// ************  TTM  ************
// subsystem           abbreviation
// ------------        ------------
//   AsmLink             A0, A1, A2, A3 or Asm
//   Backplane           BK or Back
//   Clocking            CK
//   Power               PW or PWR
 
 
class CM_Root : public TRootModule {
public:
// root-level module has no ports
 
// instantiate subsystems
  CM_AsmLink          AsmLink[ 4 ];
  CM_Backplane        Backplane;
  CM_Clocking         Clocking;
  CM_Power            Power;
 
 
 
  virtual void Register() {
// subsystems                                               // first few letters of reference designators
    rega( AsmLink, 4      );  AsmLink[ 0 ].SetReferenceBase(   "A0" );
                              AsmLink[ 1 ].SetReferenceBase(   "A1" );
                              AsmLink[ 2 ].SetReferenceBase(   "A2" );
                              AsmLink[ 3 ].SetReferenceBase(   "A3" );
    reg(  Backplane       );  Backplane.SetReferenceBase(      "BK" );
    reg(  Clocking        );  Clocking.SetReferenceBase(       "CK" );
    reg(  Power           );  Power.SetReferenceBase(          "PW" );
  }
 
  virtual void Connect() {
 
// *** connect subsystem ports (except power ports) *** //
 
  // net names to override subsequently assigned net names
  // (none for this design at this level)
 
  // AsmLink's
    for ( int a = 0; a < 4; ++ a ) {
                Backplane.Asm[ a ]  <<  AsmLink[ a ].Back;
      "CK"  <<   Clocking.Asm[ a ]  <<  AsmLink[ a ].CK;
    }
 
 
 
  // Backplane
    "BPWR_"  <<  Backplane.Power   <<  Power.BK;
    "BK_"    <<  Backplane.CK      <<  Clocking.BK;
    "RAW_TX" <<  Backplane.RAW_TX;                       // only for readable net name
 

  // Clocking
  //""       <<  Clocking.PWR      <<  Power.CK;
 
  // Power
  //"PC_"    <<  Power.VME         <<  VME_Interface.PWR;
 
 
// *** connect supply ports ***
    wireall( "VCC"  );
    wireall( "GND" );
  }
};
 
#endif