CBOLD TTM Example Design: ttm

Coolquest, Inc.
C⁺⁺BOLD Example Design: TTM
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// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _TTM_ClockingH_
#define _TTM_ClockingH_
 
#include "clockdriverscdc.h"
#include "std_drivers.h"
#include "lvds.h"
#include "sn74cbtlv3253.h"
 
// Clock Generation subsystem
 
// All necessary decoupling capacitors are already included.  See table below.
 
// nomenclature note:
//   BK only applies to the interface to the Backplane subsystem
//   BP applies to components and signals within the Clock Generation subsystem that are related to the Backplane subystem
//   FP applies to components and signals within the Clock Generation subsystem that are related to the Front Panel
 
 
 
// CB_Asm_CK: interface between AsmLink's and ClockGeneration
class CB_Asm_CK : public TBundle {
public:
 
  port TXCLK;    // to TX TXCLK
  port RXCLK_A;  // to RX REFCLK
  port RXCLK_B;
 
  virtual void Register() {
    reg( TXCLK  );
    reg( RXCLK_A );
    reg( RXCLK_B );
  }
};
 
 
 
// CB_Back_CK: interface between Backplane and ClockGeneration
class CB_Back_CK : public TBundle {
public:
 
  port RCLKOP;    // outputs from ROD (inputs from backplane) (CM range = -2 to 4.4V --> compatible with ECL, PECL, LVDS)
  port RCLKON;
  port OSC_EN;    // TTM oscillator enable from ROD -- ROD must drive this low to use RCLK
  port TEST_CLK;  // RCLK output to header, e.g., for logic analyzer
 
  virtual void Register() {
    reg( RCLKOP );
    reg( RCLKON );
    reg( OSC_EN );
    reg( TEST_CLK );
  }
};
 
 
 
 
class CM_Clocking : public TModule {  // Clocking subsystem
public:
// ***** member bundles ***** //
  CB_Asm_CK    Asm[ 4 ];  // interface to AsmLink's
  CB_Back_CK   BK;        // interface to Backplane
 
 
 
// ***** member ports ***** //
  port VCC;      // 3.3V
  port GND;
 
// ***** member modules and parts ***** //
 
  CP_XOSC_40M       OscT_BASE;         // thru-hole oscillators are wired in parallel with...
  CP_XOSC_SMT_40M   OscS_BASE;         // ... surface-mount oscillators
  CP_R30            STerm_Osc_BASE;    // series termination for oscillator outputs (they drive capacitive loads)
 
  CP_SN74CBTLV3253  Mux_RCLK;          // FET multiplexer selects between RCLK (from ROD) and oscillator
  CP_CDC2516        Drv_RCLK;          // PLL clock driver
  CP_SN65LVDS9637B  Rcv_BP_RCLKO;      // backplane and front panel differential clock receivers (LVDS, PECL, ECL)
  CP_R110           DTerm_BP_RCLKO;     // differential termination for input of clock receivers--installation of these terminators is optional
  CP_R30            STerm_BP_RCLKO;     // series termination for output of clock receivers (always installed)
 
  CP_R4_7K          PullupOsc_OUT;     // pullup in case Osc_BASE output is floated
 
  enum { ferrite_count =  2                 };    // ferrites for PLL drivers and oscillators
  enum { avc_cdc_count =  ferrite_count + 1 };    // one extra CDC for each duplicate oscillator
 
  CP_FERRITE120     Ferrite[  ferrite_count ];    // filters            for CDC25xx AVCC, W-170 AVCC, oscillator AVCC
  CP_CDC_POS        AVCC_CDC[ avc_cdc_count ];
 
//  Standard Decoupling
//  ----------------------------------------------
//  oscillators:     0  AVCC_CDC used
//  mux's            1  1 CDC *  1 chip
//  CDC2516          4  4 CDC *  1 chip
//  SN65LVDS9637B    1  1 CDC *  1 chips
//  ----------------------------------------------
//  Total CDC's      6
//  Total TDC's:     1 (arbitrary number)
 
  enum { vc_cdc_count =  6,
         vc_tdc_count =  1 };
  CP_CDC_POS  VC_CDC[ vc_cdc_count ];    // ceramic decoupling
  CP_TDC_POS  VC_TDC[ vc_tdc_count ];    // tantalum decoupling
 
 
  virtual void Register() {
// bundles
    rega( Asm, 4 );
    reg( BK );
 
// ports
    reg( VCC );
    reg( GND );
 
// parts and modules
 
    reg( OscT_BASE );
    reg( OscS_BASE );
    reg( STerm_Osc_BASE );
 
    reg( Mux_RCLK );
    reg( Drv_RCLK );
    reg( Rcv_BP_RCLKO );
    reg( DTerm_BP_RCLKO );
    reg( STerm_BP_RCLKO );
 
    reg( PullupOsc_OUT );
 
    rega( Ferrite,  ferrite_count );
    rega( AVCC_CDC, avc_cdc_count );
 
    rega( VC_CDC, vc_cdc_count );
    rega( VC_TDC, vc_tdc_count );
  }
 
  void ConnectDefault( CP_SN74CBTLV3253& Mux ) {   // wiring that is similar for several components
    GND        << Mux.OE1_N  << Mux.OE2_N;         // always OE'd
    merge( GND,   Mux.B2 );                        // mux 2 never used
    "/NC"      << Mux.A2;
  }
 
 
  virtual void Connect() {
    wireall( VCC );
    wireall( GND );
    wireall( GND, "AGND" );   // CDC25xx parts have AGND pins
 
    for ( int i = 0; i < vc_cdc_count; ++ i )  VCC << VC_CDC[ i ].POS;
    for ( int i = 0; i < vc_tdc_count; ++ i )  VCC << VC_TDC[ i ].POS;
 
    // crystal oscillators and all devices containing PLL:  wire AVCC via ferrite bead, include CDC
    int f = 0;
    VCC  ^  Ferrite[ f ]  ^  "AVCC0"   <<  AVCC_CDC[ f ].POS  <<   Drv_RCLK.AVCC;  f++;
    VCC  ^  Ferrite[ f ]  ^  "AVCC1"   <<  AVCC_CDC[ f ].POS  <<  OscT_BASE.AVCC;  f++;
                             "AVCC1"   <<  AVCC_CDC[ f ].POS  <<  OscS_BASE.AVCC;  f++;
 
// oscillator outputs via series termination:
// install only one oscillator (OscT... or OscS...)
    "OSC_BASE"  ^  STerm_Osc_BASE  ^  "LOC_OSC_BASE" << OscT_BASE.OUT << OscS_BASE.OUT  ^ PullupOsc_OUT ^  VCC;
 
    BK.OSC_EN  <<  OscT_BASE.OE  <<  OscS_BASE.OE;   // oscillator .OE's enable outputs when high, else float
 
 
// input clock with differential input termination and series output termination
    Rcv_BP_RCLKO.IN_P1  << BK.RCLKOP  << DTerm_BP_RCLKO.A;     // default:  install terminator
    Rcv_BP_RCLKO.IN_N1  << BK.RCLKON  << DTerm_BP_RCLKO.B;
 
    "BP_RCLKO"  ^ STerm_BP_RCLKO ^  "LOC_BP_RCLKO" << Rcv_BP_RCLKO.OUT1;
 
    "/NC" << Rcv_BP_RCLKO.IN_P2;   // one half of dual receiver is not used
    "/NC" << Rcv_BP_RCLKO.IN_N2;
    "/NC" << Rcv_BP_RCLKO.OUT2;
 
 
// RCLK mux
    ConnectDefault( Mux_RCLK );                 // misc. grounds and NC's
 
    Mux_RCLK.B1(  0 )  <<  "BP_RCLKO";          // RCLK from ROD
    Mux_RCLK.B1(  1 )  <<  GND;
    Mux_RCLK.B1(  2 )  <<  GND;
    Mux_RCLK.B1(  3 )  <<  "OSC_BASE";          // from oscillator
    Mux_RCLK.A1        <<  "DRVIN_RCLK";        // to driver
    Mux_RCLK.S(   1 )  <<  BK.OSC_EN;           // input select: either 0 or 3
    Mux_RCLK.S(   0 )  <<  BK.OSC_EN;
 
 
// **** driver ****
                                                          // >>> match within 3 inches length of clock nets driven by Drv_RCLK.OUT[] Drv_RCLK.FBOUT
                                                          // >>> place Drv_RCLK in a central location
    "DRVIN_RCLK"  <<  Drv_RCLK.IN;                        // from mux
    "FB_RCLK"     <<  Drv_RCLK.FBOUT  <<  Drv_RCLK.FBIN;  // driver feedback
    merge( VCC, Drv_RCLK.G );                             // enable all outputs
 
 
 
    // connect clocks to interfaces to other subsytems
    int i = 0;
    for ( int a = 0; a < 4; ++ a ) {
      Asm[ a ].RXCLK_A  <<  Drv_RCLK.OUT( i++ );
      Asm[ a ].RXCLK_B  <<  Drv_RCLK.OUT( i++ );
      Asm[ a ].TXCLK    <<  Drv_RCLK.OUT( i++ );
      if ( a == 3 )  break;                        // leave one output for TEST_CLK
      "/NC"             <<  Drv_RCLK.OUT( i++ );
    }
    BK.TEST_CLK  <<  Drv_RCLK.OUT( 15 );           // test clock to header
  }
};
 
#endif
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