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// THIS FILE IS IN THE PUBLIC DOMAIN. // IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT // NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. #ifndef _VMED_PLDH_ #define _VMED_PLDH_ class CM_VMED_PLD : public TModule { public: //Bundles CB_JTAG JT; //Define ports port HARDRESET_N; port A; //VME Address Bus (Buffered) port D; //VME Data Bus (Buffered) port LD; //Local Data Bus (32-bits wide) port LDBW; //Local Data Bus (8-bits wide, to Flash Memories) port VMEDOE_N; //Output Enable for VME Data Bus port VDATACLKEN_N; //Clock Enable for VME Data Bus (When reading/writing to/from Data Bus) port RW_N; //Read/Write Signal, indicates direction of VME transaction port LDOE_N; //Local Data Bus Output Enables (one for both) port VMEAOE_N; //Output Enable for VME Address Bus (used in 64-bit VME reads) port VASEL; //Address Bus Select (used primarily in VME64 transactions) port VLDSEL; //Local Data Bus Select between byte-wide and word-wide port CLKIN; //System Clock port VCC; //Power and Ground port GND; port VADDRCLKEN_N; //Clock Enable for VME Address Bus (again used primarily in VME64 transactions) //Instantiate parts CP_XC95144XL_144 Cpld; virtual void Register() { //Register function //Register bundles reg ( JT ); //Register all ports reg ( HARDRESET_N ); regb( A, 31, 0 ); regb( D, 31, 0 ); regb( LD, 31, 0 ); regb( LDBW, 7, 0 ); reg ( VMEDOE_N ); reg ( VDATACLKEN_N ); reg ( RW_N ); reg ( LDOE_N ); reg ( VMEAOE_N ); reg ( VASEL ); reg ( VLDSEL ); reg ( CLKIN ); reg ( VCC ); reg ( GND ); reg ( VADDRCLKEN_N ); //Register all instantiated parts and modules reg( Cpld ); } virtual void Connect() { //Connect function wire ( JT, Cpld ); //Connections to ports conn ( A(31), Cpld.IO79 ); conn ( A(30), Cpld.IO80 ); conn ( A(29), Cpld.IO81 ); conn ( A(28), Cpld.IO82 ); conn ( A(27), Cpld.IO83 ); conn ( A(26), Cpld.IO85 ); conn ( A(25), Cpld.IO86 ); conn ( A(24), Cpld.IO87 ); conn ( A(0), Cpld.IO88 ); conn ( A(1), Cpld.IO91 ); conn ( A(2), Cpld.IO92 ); conn ( A(3), Cpld.IO93 ); conn ( A(4), Cpld.IO94 ); conn ( A(5), Cpld.IO95 ); conn ( A(6), Cpld.IO96 ); conn ( A(7), Cpld.IO97 ); conn ( A(8), Cpld.IO98 ); conn ( A(9), Cpld.IO100 ); conn ( A(10), Cpld.IO101 ); conn ( A(11), Cpld.IO102 ); conn ( A(12), Cpld.IO103 ); conn ( A(13), Cpld.IO104 ); conn ( A(14), Cpld.IO105 ); conn ( A(15), Cpld.IO106 ); conn ( A(16), Cpld.IO107 ); conn ( A(17), Cpld.IO110 ); conn ( A(18), Cpld.IO111 ); conn ( A(19), Cpld.IO112 ); conn ( A(20), Cpld.IO113 ); conn ( A(21), Cpld.IO115 ); conn ( A(22), Cpld.IO116 ); conn ( A(23), Cpld.IO117 ); conn ( D(31), Cpld.IO57 ); conn ( D(30), Cpld.IO58 ); conn ( D(29), Cpld.IO59 ); conn ( D(28), Cpld.IO60 ); conn ( D(27), Cpld.IO61 ); conn ( D(26), Cpld.IO64 ); conn ( D(25), Cpld.IO66 ); conn ( D(24), Cpld.IO68 ); conn ( D(23), Cpld.IO69 ); conn ( D(22), Cpld.IO70 ); conn ( D(21), Cpld.IO71 ); conn ( D(20), Cpld.IO74 ); conn ( D(19), Cpld.IO75 ); conn ( D(18), Cpld.IO76 ); conn ( D(17), Cpld.IO77 ); conn ( D(16), Cpld.IO78 ); conn ( D(15), Cpld.IO118 ); conn ( D(14), Cpld.IO119 ); conn ( D(13), Cpld.IO120 ); conn ( D(12), Cpld.IO121 ); conn ( D(11), Cpld.IO124 ); conn ( D(10), Cpld.IO125 ); conn ( D(9), Cpld.IO126 ); conn ( D(8), Cpld.IO128 ); conn ( D(7), Cpld.IO129 ); conn ( D(6), Cpld.IO130 ); conn ( D(5), Cpld.IO131 ); conn ( D(4), Cpld.IO132 ); conn ( D(3), Cpld.IO133 ); conn ( D(2), Cpld.IO134 ); conn ( D(1), Cpld.IO135 ); conn ( D(0), Cpld.IO136 ); conn ( LD(31), Cpld.IO4 ); conn ( LD(30), Cpld.IO7 ); conn ( LD(29), Cpld.IO9 ); conn ( LD(28), Cpld.IO10 ); conn ( LD(27), Cpld.IO11 ); conn ( LD(26), Cpld.IO12 ); conn ( LD(25), Cpld.IO13 ); conn ( LD(24), Cpld.IO14 ); conn ( LD(23), Cpld.IO15 ); conn ( LD(22), Cpld.IO16 ); conn ( LD(21), Cpld.IO17 ); conn ( LD(20), Cpld.IO19 ); conn ( LD(19), Cpld.IO20 ); conn ( LD(18), Cpld.IO21 ); conn ( LD(17), Cpld.IO22 ); conn ( LD(16), Cpld.IO23 ); conn ( LD(15), Cpld.IO24 ); conn ( LD(14), Cpld.IO25 ); conn ( LD(13), Cpld.IO26 ); conn ( LD(12), Cpld.IO27 ); conn ( LD(11), Cpld.IO28 ); conn ( LD(10), Cpld.IO31 ); conn ( LD(9), Cpld.IO33 ); conn ( LD(8), Cpld.IO34 ); conn ( LD(7), Cpld.IO35 ); conn ( LD(6), Cpld.IO39 ); conn ( LD(5), Cpld.IO40 ); conn ( LD(4), Cpld.IO41 ); conn ( LD(3), Cpld.IO43 ); conn ( LD(2), Cpld.IO44 ); conn ( LD(1), Cpld.IO45 ); conn ( LD(0), Cpld.IO46 ); conn ( LDBW(7), Cpld.IO48 ); conn ( LDBW(6), Cpld.IO49 ); conn ( LDBW(5), Cpld.IO50 ); conn ( LDBW(4), Cpld.IO51 ); conn ( LDBW(3), Cpld.IO52 ); conn ( LDBW(2), Cpld.IO53 ); conn ( LDBW(1), Cpld.IO54 ); conn ( LDBW(0), Cpld.IO56 ); wire ( VMEDOE_N, "IO2_GTS3" ); wire ( VDATACLKEN_N, "IO137" ); wire ( RW_N, "IO138" ); wire ( LDOE_N, "IO5_GTS1" ); wire ( VMEAOE_N, "IO3_GTS4" ); wire ( VASEL, "IO139" ); wire ( VLDSEL, "IO140" ); wire ( CLKIN, "IO30_GCK1" ); wire ( VADDRCLKEN_N, "IO142" ); wire ( HARDRESET_N, "IO143_GSR" ); //Internal connections conn ( "/NC", Cpld.IO6_GTS2, Cpld.IO32_GCK2, Cpld.IO38_GCK3 ); //Wire-all connections wire( VCC ); //Connect VCC to upper level wire( VCC, "VCCIO" ); //VCCIO is 3.3V for this application wire( GND ); //Connect GND to upper level } }; #endif
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