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C++BOLD Example Design: IROD

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _STD_FIFOH_
#define _STD_FIFOH_
 
#include "idt72v3690.h"
 
// All necessary FIFO decoupling capacitors are provided in this class.
 
// 32-bit FIFO using IDT standard timing mode
 
class CM_STD_FIFO : public TModule {    // base class for all FIFO's on the ROD motherboard
 
public:
// ***** member bundles ***** //
 
// ***** member ports ***** //
  port VCC;     // 3.3V
  port GND;
 
  port D;       // 32 bits of data, remaining 4 bits are tied low
  port Q;
 
  port RD_CLK;  // renamed from RCLK (to avoid confusion with ROD's RCLK)
  port WR_CLK;  // renamed from WCLK
 
  port MRS_N;   // master reset
  port OE_N;    // output enable for Q's
  port WEN_N;   // write enable
  port REN_N;   // read enable
  port LD_N;    // load for loading offsets for PAE and PAF, also used with FS0, FS1 to set default offsets at reset
 
  port EF_N;    // connected to FIFO's EF_N_OR_N pin, which means EF_N in IDT standard mode
  port PAE_N;   // programmable almost empty flag
  port PAF_N;   // programmable almost full flag
 
 
 
// ***** member modules and parts ***** //
 
  CP_IDT72V3690    Fifo;
 
  // decoupling
  enum { vc_cdc_count =  11,
         vc_tdc_count =  1 };
  CP_CDC_POS  VC_CDC[ vc_cdc_count ];    // ceramic decoupling
  CP_TDC_POS  VC_TDC[ vc_tdc_count ];    // tantalum decoupling
 
 
  virtual void Register() {
 
// bundles
// ports
    reg(  VCC );
    reg(  GND );
    regb( D, 31, 0 );
    regb( Q, 31, 0 );
 
    reg(  RD_CLK );
    reg(  WR_CLK );
 
    reg(  MRS_N  );
    reg(  OE_N   );
    reg(  WEN_N  );
    reg(  REN_N  );
    reg(  LD_N   );
 
    reg(  EF_N   );
    reg(  PAE_N  );
    reg(  PAF_N  );
 
 
// parts and modules
    reg(  Fifo );
 
    rega( VC_CDC, vc_cdc_count );
    rega( VC_TDC, vc_tdc_count );
 
  }
 
  virtual void Connect() {
    VCC << Fifo.VCC;
    for ( int i = 0; i < vc_cdc_count; ++ i )  VCC << VC_CDC[ i ].POS;
    for ( int i = 0; i < vc_tdc_count; ++ i )  VCC << VC_TDC[ i ].POS;
 
    wireall( GND );
    wire( "/NC", "NC" );
 
    D << Fifo.D( 31, 0 );   // 32-bit FIFO
    Q << Fifo.Q( 31, 0 );
 
 
    wire( RD_CLK, "RCLK" );   // these are renamed to avoid confusion with ROD's RCLK
    wire( WR_CLK, "WCLK" );
 
    wire( MRS_N );
    wire( OE_N  );
    wire( WEN_N );
    wire( REN_N );
    wire( LD_N );
 
    wire( EF_N, "EF_N_OR_N" );       // FIFO's EF_N_OR_N pin means EF_N in IDT standard mode
    wire( PAE_N );
    wire( PAF_N );
 
    wire( LD_N );
 
                            // the following should not change after master reset
    GND << Fifo.OW;         // output width             --> 36 in x 36 out
    GND << Fifo.IW;         // input width              -->  "
    GND << Fifo.BM;         // bus matching             -->  "
 
    VCC << Fifo.BE_N;       // big endian               --> little endian (not relevant because in and out are the same width)
    VCC << Fifo.RM;         // retransmit timing mode   --> zero latency retransmit (not used)
    GND << Fifo.PFM;        // programmable flag mode   --> asynchronous programmable flags
    GND << Fifo.IP;         // interspersed parity      --> non-interspersed parity (no parity, only D0-D31 are relevant when loading flag offsets)
    GND << Fifo.FS0;        // flag select              --> default offset of 1023 (LD_N high) or 127 (LD_N low) for programmable flags
    GND << Fifo.FS1;
 
                            // the following control signals are not used
    GND << Fifo.FWFT_SI;    // first word fall through / serial in  --> IDT standard mode, serial input not used
    VCC << Fifo.PRS_N;      // partial reset                        --> no partial reset
    VCC << Fifo.RT_N;       // retransmit                           --> no retransmit
    VCC << Fifo.SEN_N;      // serial enable                        --> no serial loading of offset registers
 
                                     // unused flags and data
    "/NC" <<      Fifo.HF_N;         // half-full flag
    "/NC" <<      Fifo.FF_N_IR_N;    // full flag/input ready
    merge( GND,   Fifo.D(35, 32) );  // data
    merge( "/NC", Fifo.Q(35, 32) );
 
  }
};
 
#endif