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C++BOLD Example Parts Library

$INSERT
// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
$END
 
// Part file for Spartan 2 FPGA - FG256 package
// due to obsolescence of Spartan 2 series, this file is particular to the task at hand--many FPGA features are omitted
 
$PART_NAME XC2S150_FG256
$JEDEC_TYPE FG256
$REF_PREFIX U
$PIN_COUNT 256
$PORTS
 
  // JTAG and configuration
  TCK       C4;
  TMS       D3;
  TDI       A15;
  TDO       B14;
 
  PROGRAM_N P15;
  CCLK      D15;
  DIN       D14;  // also user I/O
  DOUT      C15;  // also BUSY, user I/O
 
  INIT_N    N15;  // also user I/O
  DONE      R14;
  M0        N3;
  M1        P2;
  M2        R3;
 
  // Global Clocks
  GCLK0      N8;
  GCLK1      R8;
  GCLK2      C9;
  GCLK3      B8;
 
  // User I/O
  // pins are ordered to ~match pin arrangement of T__XC2S150_PQ208
  // pin order 0:N matches Xilinx pinout tables reading down
  BANK7[0:22]  C2  A2  B1  E3  D2  C1  F3  E2  E4  D1
               E1  F2  G3  F1  F4  F5  G2  H3  G4  H2
               G5  H4  G1;
 
  BANK6[0:22]  J2  H1  J4  J1  J3  K5  K2  K1  K3  L1
               L2  K4  M1  L4  M2  L3  N1  P1  L5  N2
               M4  R1  M3;
 
  BANK5[0:18]  N5  T2  P5  T3  T4  M6  T5  N6  R5  P6
               R6  M7  N7  T6  P7  P8  R7  T7  T8;
 
  BANK4[0:21]  N9  R9  N10 T9  P9  M10 R10 P10 T10 R11
               M11 T11 N11 R12 P11 T12 T13 N12 R13 P12
               P13 T14;
 
  BANK3[0:21]  N14 T15 M13 R16 M14 L14 M15 L12 P16 L13
               N16 M16 K14 L16 K13 L15 K12 K16 J16 J14
               K15 J15;
 
  BANK2[0:21]  H16 H14 H15 J13 G16 H13 G14 G15 G12 F16
               G13 F15 E16 F14 D16 F12 E15 F13 E14 C16
               E13 B16;
 
  BANK1[0:21]  B13 C13 C12 A14 D12 B12 C11 A13 D11 A12
               E11 B11 A11 C10 B10 D10 A10 B9  E10 A9
               D9  A8;
 
  BANK0[0:19]  A7  D8  A6  B7  C8  D7  E7  C7  B6  A5
               C6  B5  D6  A4  B4  E6  D5  A3  C5  B3;
 
 
 
  // Power and ground
  GND[36]       A1  A16 B2  B15 F6  F7  F10 F11 G6  G7
                G8  G9  G10 G11 H7  H8  H9  H10 J7  J8
                J9  J10 K6  K7  K8  K9  K10 K11 L6  L7
                L10 L11 R2  R15 T1  T16;
 
  VCCINT[12]    C3  C14 D4  D13 E5  E12 M5  M12 N4  N13
                P3  P14;
                
//VCC[16]       E8  F8  E9  F9  H11 H12 J11 J12 L9  M9
//              L8  M8  J5  J6  H5  H6;
 
  VCCO0[2]      E8  F8;
  VCCO1[2]      E9  F9;
  VCCO2[2]      H11 H12;
  VCCO3[2]      J11 J12;
  VCCO4[2]      L9  M9;
  VCCO5[2]      L8  M8;
  VCCO6[2]      J5  J6;
  VCCO7[2]      H5  H6;
 
  NC[2]         P4  R4;  // formerly PWDN_N and STATUS
 
$ENDPORTS
$ENDPART