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C++BOLD Example Parts Library

$INSERT
// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
$END
 
// TI DSP Emulator Header Part File
 
$PART_NAME   EMU_HEADER
$JEDEC_TYPE  HEADER7X2RT_100MIL
$REF_PREFIX  H
$PIN_COUNT   14
$PORTS
  KEY         6 ;   // missing pin:   no-connect
  PD          5 ;   // power-detect:  attach to VCC
  TMS         1 ;
  TDI         3 ;
  TDO         7 ;
  TCK        11 ;
  TRST_N      2 ;
  EMU0       13 ;
  EMU1       14 ;
  TCK_RET     9 ;
  GND[4]      4 8 10 12 ;
$ENDPORTS
$ENDPART
 
 
// there does not seem to be a standard for JTAG connector
// --> use something like the connector for NIKHEF's LPT_JTAG:
//
//  1 TCK      2 BYPASS_N    
//  3 TMS      4 GND
//  5 TDI      6 VCC
//  7 TDO      8 GND
//  9 TRST_N  10 P_ENA
    
$PART_NAME   JTAG_HEADER
$JEDEC_TYPE  HEADER5X2RT_100MIL
$REF_PREFIX  H
$PIN_COUNT   10
$PORTS
  TCK        1 ;   // output from POD to   motherboard
  TMS        3 ;   // output from POD to   motherboard
  TDI        5 ;   // output from POD to   motherboard
  TDO        7 ;   // input to    POD from motherboard
  TRST_N     9 ;   // not normally used
  BYPASS_N   2 ;   // not normally used
  P_ENA     10 ;   // not normally used
  VCC         6 ;  // 3.3V typ from motherboard to POD
  GND[2]    4 8 ;
$ENDPORTS
$ENDPART
 
 
// safety interlock header
// choose pinout such that JTAG pod would not be damaged if connected to interlock header
// interlock driver outputs can withstand short to ground
//  JTAG      INTLK   INTLK   JTAG
//  --------  ------  ------  -----------
//  1 TCK     NC      GND     2  BYPASS_N
//  3 TMS     IN0     OUT1    4  GND
//  5 TDI     NC      GND     6  VCC
//  7 TDO     IN1     GND     8  GND
//  9 TRST_N  OUT0    GND     10 P_ENA
    
$PART_NAME   INTLK_HEADER
$JEDEC_TYPE  HEADER5X2RT_100MIL
$REF_PREFIX  H
$PIN_COUNT   10
$PORTS
  IN[1:0]     7 3;
  OUT[1:0]    4 9;
  NC[2]       1 5;
  GND_JMP[4]  2 6 8 10;   // connect to GND via jumper --> cable ground can be isolated
$ENDPORTS
$ENDPART
 
 
$PART_NAME   TXIO_HEADER       // for CTM
$JEDEC_TYPE  HEADER8X2RT_100MIL
$REF_PREFIX  H
$PIN_COUNT   16
$PORTS
  IN[1:0]     3  1;        // two inputs to all Tx FPGA's
  OUT0_[1:0]  7  5;        // two outputs from each Tx FPGA
  OUT1_[1:0] 11  9;
  OUT2_[1:0] 15 13;
  GND[8]      2  4  6 8 10 12 14 16;
$ENDPORTS
$ENDPART
 
    
$PART_NAME   TTC_HEADER       // for ROD
$JEDEC_TYPE  HEADER8X2RT_100MIL
$REF_PREFIX  H
$PIN_COUNT   16
$PORTS
  RCLKIP  3;   // clock inputs
  RCLKIN  4;
 
  TCLKIP  7;
  TCLKIN  8;
 
  TTC0P  11;   // general-purpose inputs to TTC FPGA, e.g., L1 trigger
  TTC0N  12;
 
  TTC1P  13;
  TTC1N  14;
 
  GND[8]      1  2  5  6  9 10 15 16;
$ENDPORTS
$ENDPART