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C++BOLD Example Parts Library

$INSERT
// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
$END
 
// Part File for Generic Processing Unit (DSP Module) Connector
 
$PART_NAME GPU_CONN
$JEDEC_TYPE GPUCONN   // GPUCONN includes 30X10 connector and four mounting holes
$REF_PREFIX GP
$PIN_COUNT 300
$PORTS
    CE0_N G21;
    CE1_N G20;
    CE2_N G19;
    CE3_N G18;
    AWE_N G15;
    ARE_N G17;
    AOE_N G16;
    ARDY G13;
    DX0 D24;
    DR0 E22;
    CLKX0 E28;
    CLKR0 E30;
    CLKS0 E29;
    FSX0 E25;
    FSR0 E27;
    FTDO A3;
    FDOUT D4;
    FINIT_N E10;
    FCCLK C5;
    FDONE E13;
    FPROGRAM_N C11;
    FM0 F17; 
    FM1 F16;
    FM2 F15;
    FTMS C14;
    FTDI A2;
    FTCK C13;
    FDIN D5;
    EFDOUT H11;
    EFINIT_N H10;
    EFDONE H9;
    EFPROGRAM_N D3;
    EMU0 D17;
    EMU1 G25;
    TMS G23;
    TDI G29;
    TCK G30;
    TRST_N G24;
    TDO I27;
    GEN[0:76] B29 B28 A29 A27 B30 B26 A30 A26 A28 B25 B24 B27 A25 B23 B22 A23
              A24 B21 A22 B20 A21 B19 A19 A20 B18 B16 A18 A17 A16 B17 B15 A15
              B2 A4 B1 C6 A1 A6 E7 D22 D23 E19 E23 F27 D18 E21 D19 E20
              D16 E14 H27 E15 D12 E16 G27 B13 C9 C12 A10 D11 B14 A9 A14 C7
              A12 A7 C8 A11 C10 A8 A5 C4 E4 E24 E26 D25 G28 ;
    EGEN[0:74] J10 J11 J15 J9 J14 J17 J12 J13 J20 J16 J19 J18 J23 J22 J21 I24
               J24 I23 I22 I21 I20 I19 I18 I15 I17 I13 I14 I16 I11 I10 I12 I9
               J8 J7 I7 J6 I8 I6 H3 J1 J5 H4 I5 I4 I1 J4 I2 I3 
               J2 J3 H8 H7 H6 H5 H2 H1 G1 E1 E2 C1 C2 G8 F1 G7 
               F2 G6 G5 F7 F6 G4 F5 G3 F4 F3 G2 ;
    XCLKIN J29;
    CLKIN J27;
    RESET_N G22;
    RCLK I29;
    SCLK H29;
    EGCK0 F11;
    EGCK1 F10;
    GND[69] B7 B8 D1 D2 D8 D9 D14 D15 D20 D21 D26 D27 C3 C15 C16 C17
            C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 E3 E5 E6
            E8 E9 E11 E12 E17 E18 F8 F9 F14 F18 F19 F20 F26 G14 G26 H12
            H13 H14 H15 H16 H17 H18 H21 H22 H23 H24 H25 H26 H28 H30 I25 I26
            I28 I30 J26 J28 J30 ; 
    VCC[10] D6 D7 D10 D13 D28 D29 D30 F12 H19 H20 ;
    VCORE[8] F21 F22 F23 F24 F25 F28 F29 F30;
    VCCINT[8] B3 B4 B5 B6 B9 B10 B11 B12;
    VREF F13;
    NC[5] A13 G9 G10 G11 G12;
    PRESENT J25;
$ENDPORTS
$ENDPART