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C++BOLD Example Parts Library

$INSERT
// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
$END
 
// part file for clock drivers, e.g., CDC series from TI
 
// TI 10-output non-pll driver
 
$PART_NAME CDC319
$JEDEC_TYPE SSOP28
$REF_PREFIX U
$PIN_COUNT 28
$PORTS
  OUT[9:0]  2  3  6  7       // output pins of byte 0
           22 23 26 27       // output pins of byte 1
           11 18;            // output pins of byte 2
  IN 9;                      // input
  OE 20;                     // output enable (active high, internal pullup)
  VCC[7] 1 5 10 13 19 24 28;
  GND[7] 4 8 12 16 17 21 25;
  SCLOCK 15;                 // serial clock (internal pullup)
  SDATA 14;                  // bidirectional serial data (internal pullup)
$ENDPORTS
$ENDPART
 
 
// TI 10-output PLL clock driver
 
$PART_NAME CDC2510
$JEDEC_TYPE TSSOP24
$REF_PREFIX U
$PIN_COUNT 24
$PORTS
  IN       24;               // "CLK"
  OUT[9:0] 21 20 17 16 15    // "1Y9 - 1Y0"
            9  8  5  4  3;
  FBOUT    12;
  FBIN     13;
  G        11;               // output enable, no pullup (low --> outputs driven low)
  AVCC     23;
  VCC[4]    2 10 14 22;
  AGND      1;
  GND[4]    6  7 18 19;
$ENDPORTS
$ENDPART
 
 
// TI 16-output PLL clock driver
 
$PART_NAME CDC2516
$JEDEC_TYPE SSOP48    // TI's DGG package
$REF_PREFIX U
$PIN_COUNT 48
$PORTS
  IN         12;            // "CLK"
  OUT[15:0]  42 43 46 47    // "4Y3 - 4Y0"
             26 27 30 31    // "3Y3 - 3Y0"
             23 22 19 18    // "2Y3 - 2Y0"
              7  6  3  2;   // "1Y3 - 1Y0"
  FBOUT      35;
  FBIN       37;
  G[3:0]     40 33 16 9;    // "4G - 1G" output enable, no pullup (low --> outputs driven low)
  AVCC[2]    11 38;
  VCC[8]      1  8 17 24
             25 32 41 48;
  AGND[3]    13 14 36;
  GND[12]     4  5 10 15 20 21
             28 29 34 39 44 45;
$ENDPORTS
$ENDPART
 
 
// TI 10-output LVDS non-PLL clock driver
 
$PART_NAME CDCLVD110
$JEDEC_TYPE TQFP32
$REF_PREFIX U
$PIN_COUNT 32
$PORTS
  CK          1;
  SI          2;
  EN          8;
  CLK0_P      3;
  CLK0_N      4;
  CLK1_P      6;
  CLK1_N      7;
 
  Q[19:0]    10 11 12 13 14 15          // noninverting outputs at even indexes and inverting outputs at odd indexes
             17 18 19 20 21 22 23 24
             26 27 28 29 30 31;
  VBB         5;                        // 1.25V reference output
  VDD[1:0]   16 32;                     // bus --> each pin can have its own ferrite/cap filter
  GND[2]      9 25;                     // VSS on data sheet
$ENDPORTS
$ENDPART