Backplane.BAP1 BK P 1 Backplane.BAP2 BK P 2 Backplane.BAP0 BK P 0 Backplane.BAP5 BK P 5 Backplane.BAP6 BK P 6 Backplane.V5_CDC0 BK K 1 Backplane.V5_CDC1 BK K 2 Backplane.V5_CDC2 BK K 3 Backplane.V5_CDC3 BK K 4 Backplane.V5_CDC4 BK K 5 Backplane.V5_CDC5 BK K 6 Backplane.V5_CDC6 BK K 7 Backplane.V3_CDC0 BK K 8 Backplane.V3_CDC1 BK K 9 Backplane.V3_CDC2 BK K 10 Backplane.V3_CDC3 BK K 11 Backplane.V3_CDC4 BK K 12 Backplane.V3_CDC5 BK K 13 Backplane.V3_CDC6 BK K 14 Backplane.V5_TDC0 BK T 1 Backplane.V3_TDC0 BK T 2 ClockGeneration.NoisyPLD.Cpld CG U 1 ClockGeneration.NoisyPLD.VC_CDC0 CG K 1 ClockGeneration.NoisyPLD.VC_CDC1 CG K 2 ClockGeneration.NoisyPLD.VC_CDC2 CG K 3 ClockGeneration.NoisyPLD.VC_CDC3 CG K 4 ClockGeneration.NoisyPLD.VC_TDC0 CG T 1 ClockGeneration.QuietPLD.Cpld CG U 2 ClockGeneration.QuietPLD.VC_CDC0 CG K 5 ClockGeneration.QuietPLD.VC_CDC1 CG K 6 ClockGeneration.QuietPLD.VC_CDC2 CG K 7 ClockGeneration.QuietPLD.VC_CDC3 CG K 8 ClockGeneration.QuietPLD.VC_TDC0 CG T 2 ClockGeneration.OscT_HPU CG X 1 ClockGeneration.OscT_BASE CG X 2 ClockGeneration.OscT_VME CG X 3 ClockGeneration.OscS_HPU CG X 4 ClockGeneration.OscS_BASE CG X 5 ClockGeneration.OscS_VME CG X 6 ClockGeneration.STerm_Osc_HPU CG R 1 ClockGeneration.STerm_Osc_BASE CG R 2 ClockGeneration.STerm_BOOT_CLK CG R 3 ClockGeneration.Syn_RCLK.Syn CG U 3 ClockGeneration.Syn_RCLK.AC_Couple CG C 1 ClockGeneration.Syn_RCLK.SeriesTerm CG R 4 ClockGeneration.Syn_RCLK.Ferrite CG L 1 ClockGeneration.Syn_RCLK.VC_CDC0 CG K 9 ClockGeneration.Syn_RCLK.VC_CDC1 CG K 10 ClockGeneration.Syn_SCLK.Syn CG U 4 ClockGeneration.Syn_SCLK.AC_Couple CG C 2 ClockGeneration.Syn_SCLK.SeriesTerm CG R 5 ClockGeneration.Syn_SCLK.Ferrite CG L 2 ClockGeneration.Syn_SCLK.VC_CDC0 CG K 11 ClockGeneration.Syn_SCLK.VC_CDC1 CG K 12 ClockGeneration.Syn_TCLK.Syn CG U 5 ClockGeneration.Syn_TCLK.AC_Couple CG C 3 ClockGeneration.Syn_TCLK.SeriesTerm CG R 6 ClockGeneration.Syn_TCLK.Ferrite CG L 3 ClockGeneration.Syn_TCLK.VC_CDC0 CG K 13 ClockGeneration.Syn_TCLK.VC_CDC1 CG K 14 ClockGeneration.Syn_DCLK.Syn CG U 6 ClockGeneration.Syn_DCLK.AC_Couple CG C 4 ClockGeneration.Syn_DCLK.SeriesTerm CG R 7 ClockGeneration.Syn_DCLK.Ferrite CG L 4 ClockGeneration.Syn_DCLK.VC_CDC0 CG K 15 ClockGeneration.Syn_DCLK.VC_CDC1 CG K 16 ClockGeneration.Syn_DC_CLK.Syn CG U 7 ClockGeneration.Syn_DC_CLK.AC_Couple CG C 5 ClockGeneration.Syn_DC_CLK.SeriesTerm CG R 8 ClockGeneration.Syn_DC_CLK.Ferrite CG L 5 ClockGeneration.Syn_DC_CLK.VC_CDC0 CG K 17 ClockGeneration.Syn_DC_CLK.VC_CDC1 CG K 18 ClockGeneration.Syn_DX_CLK.Syn CG U 8 ClockGeneration.Syn_DX_CLK.AC_Couple CG C 6 ClockGeneration.Syn_DX_CLK.SeriesTerm CG R 9 ClockGeneration.Syn_DX_CLK.Ferrite CG L 6 ClockGeneration.Syn_DX_CLK.VC_CDC0 CG K 19 ClockGeneration.Syn_DX_CLK.VC_CDC1 CG K 20 ClockGeneration.Syn_HPU_CLK.Syn CG U 9 ClockGeneration.Syn_HPU_CLK.AC_Couple CG C 7 ClockGeneration.Syn_HPU_CLK.SeriesTerm CG R 10 ClockGeneration.Syn_HPU_CLK.Ferrite CG L 7 ClockGeneration.Syn_HPU_CLK.VC_CDC0 CG K 21 ClockGeneration.Syn_HPU_CLK.VC_CDC1 CG K 22 ClockGeneration.Syn_DPU_CLK.Syn CG U 10 ClockGeneration.Syn_DPU_CLK.AC_Couple CG C 8 ClockGeneration.Syn_DPU_CLK.SeriesTerm CG R 11 ClockGeneration.Syn_DPU_CLK.Ferrite CG L 8 ClockGeneration.Syn_DPU_CLK.VC_CDC0 CG K 23 ClockGeneration.Syn_DPU_CLK.VC_CDC1 CG K 24 ClockGeneration.Syn_DXINT_CLK.Syn CG U 11 ClockGeneration.Syn_DXINT_CLK.AC_Couple CG C 9 ClockGeneration.Syn_DXINT_CLK.SeriesTerm CG R 12 ClockGeneration.Syn_DXINT_CLK.Ferrite CG L 9 ClockGeneration.Syn_DXINT_CLK.VC_CDC0 CG K 25 ClockGeneration.Syn_DXINT_CLK.VC_CDC1 CG K 26 ClockGeneration.Mux_RCLK CG U 12 ClockGeneration.Mux_SCLK CG U 13 ClockGeneration.Mux_TCLK CG U 14 ClockGeneration.Mux_DCLK CG U 15 ClockGeneration.Mux_DC_CLK CG U 16 ClockGeneration.Mux_DX_CLK CG U 17 ClockGeneration.Mux_HPU_CLK CG U 18 ClockGeneration.Mux_SYN_BASE CG U 19 ClockGeneration.SMux_RCLK CG U 20 ClockGeneration.SMux_TCLK CG U 21 ClockGeneration.SMux_HPU_CLK CG U 22 ClockGeneration.SMux_SYN_BASE CG U 23 ClockGeneration.Mpy_IRCLK CG U 24 ClockGeneration.Mpy_ISCLK CG U 25 ClockGeneration.Mpy_ITCLK CG U 26 ClockGeneration.STerm_Mpy_IRCLK CG R 13 ClockGeneration.STerm_Mpy_ISCLK CG R 14 ClockGeneration.STerm_Mpy_ITCLK CG R 15 ClockGeneration.Drv_IRCLK.Drv CG U 27 ClockGeneration.Drv_IRCLK.Term1 CG RP 1 ClockGeneration.Drv_IRCLK.Term2 CG RP 2 ClockGeneration.Drv_ISCLK.Drv CG U 28 ClockGeneration.Drv_ISCLK.Term1 CG RP 3 ClockGeneration.Drv_ISCLK.Term2 CG RP 4 ClockGeneration.Drv_ITCLK.Drv CG U 29 ClockGeneration.Drv_ITCLK.Term1 CG RP 5 ClockGeneration.Drv_ITCLK.Term2 CG RP 6 ClockGeneration.Drv_SYN_BASE.Drv CG U 30 ClockGeneration.Drv_SYN_BASE.Term1 CG RP 7 ClockGeneration.Drv_SYN_BASE.Term2 CG RP 8 ClockGeneration.Drv_RCLK0 CG U 31 ClockGeneration.Drv_SCLK CG U 32 ClockGeneration.Drv_TCLK CG U 33 ClockGeneration.Drv_DCLK CG U 34 ClockGeneration.Drv_DC_CLK CG U 35 ClockGeneration.Drv_DX_CLK CG U 36 ClockGeneration.Drv_HPU_CLK CG U 37 ClockGeneration.Drv_DPU_CLK CG U 38 ClockGeneration.Drv_DXINT_CLK CG U 39 ClockGeneration.Drv_VME_CLK CG U 40 ClockGeneration.Drv_BP_RCLKO CG U 41 ClockGeneration.Drv_BP_SCLKO CG U 42 ClockGeneration.Drv_BP_TCLKO CG U 43 ClockGeneration.Drv_BP_DCLKO CG U 44 ClockGeneration.Rcv_BP_RCLKI CG U 45 ClockGeneration.Rcv_BP_TCLKI CG U 46 ClockGeneration.Rcv_FP_RCLKI CG U 47 ClockGeneration.Rcv_FP_TCLKI CG U 48 ClockGeneration.Drv_RCLK1 CG U 49 ClockGeneration.DTerm_BP_RCLKI CG R 16 ClockGeneration.DTerm_BP_TCLKI CG R 17 ClockGeneration.DTerm_FP_RCLKI CG R 18 ClockGeneration.DTerm_FP_TCLKI CG R 19 ClockGeneration.STerm_BP_RCLKI CG R 20 ClockGeneration.STerm_BP_TCLKI CG R 21 ClockGeneration.STerm_FP_RCLKI CG R 22 ClockGeneration.STerm_FP_TCLKI CG R 23 ClockGeneration.STerm_DERIVED_BASE CG R 24 ClockGeneration.CLC_IRCLK CG C 10 ClockGeneration.CLC_ISCLK CG C 11 ClockGeneration.CLC_ITCLK CG C 12 ClockGeneration.CLC_DC_CLK CG C 13 ClockGeneration.CLC0 CG C 14 ClockGeneration.CLC1 CG C 15 ClockGeneration.CLC2 CG C 16 ClockGeneration.CLC3 CG C 17 ClockGeneration.CLC4 CG C 18 ClockGeneration.CLC5 CG C 19 ClockGeneration.CLC6 CG C 20 ClockGeneration.CLC7 CG C 21 ClockGeneration.CLC8 CG C 22 ClockGeneration.CLC9 CG C 23 ClockGeneration.CLC10 CG C 24 ClockGeneration.CLC11 CG C 25 ClockGeneration.PulldownSyn_HPU CG R 25 ClockGeneration.PullupOsc_BASE CG R 26 ClockGeneration.PullupVB_OE CG R 27 ClockGeneration.SeriesVCOK CG R 28 ClockGeneration.Mono0 CG MP 1 ClockGeneration.Mono1 CG MP 2 ClockGeneration.Mono2 CG MP 3 ClockGeneration.Mono3 CG MP 4 ClockGeneration.Mono4 CG MP 5 ClockGeneration.Mono5 CG MP 6 ClockGeneration.Mono6 CG MP 7 ClockGeneration.Mono7 CG MP 8 ClockGeneration.Mono8 CG MP 9 ClockGeneration.Mono9 CG MP 10 ClockGeneration.Mono10 CG MP 11 ClockGeneration.Mono11 CG MP 12 ClockGeneration.Mono12 CG MP 13 ClockGeneration.Mono13 CG MP 14 ClockGeneration.Mono14 CG MP 15 ClockGeneration.Mono15 CG MP 16 ClockGeneration.Mono16 CG MP 17 ClockGeneration.Mono17 CG MP 18 ClockGeneration.Mono18 CG MP 19 ClockGeneration.Mono19 CG MP 20 ClockGeneration.Mono20 CG MP 21 ClockGeneration.Mono21 CG MP 22 ClockGeneration.Mono22 CG MP 23 ClockGeneration.Mono23 CG MP 24 ClockGeneration.Mono24 CG MP 25 ClockGeneration.Mono25 CG MP 26 ClockGeneration.Mono26 CG MP 27 ClockGeneration.Mono27 CG MP 28 ClockGeneration.Mono28 CG MP 29 ClockGeneration.Mono29 CG MP 30 ClockGeneration.Mono30 CG MP 31 ClockGeneration.Mono31 CG MP 32 ClockGeneration.Mono32 CG MP 33 ClockGeneration.Mono33 CG MP 34 ClockGeneration.Mono34 CG MP 35 ClockGeneration.Mono35 CG MP 36 ClockGeneration.Mono36 CG MP 37 ClockGeneration.Mono37 CG MP 38 ClockGeneration.Mono38 CG MP 39 ClockGeneration.Mono39 CG MP 40 ClockGeneration.Mono40 CG MP 41 ClockGeneration.Mono41 CG MP 42 ClockGeneration.Mono42 CG MP 43 ClockGeneration.Mono43 CG MP 44 ClockGeneration.Mono44 CG MP 45 ClockGeneration.Mono45 CG MP 46 ClockGeneration.Mono46 CG MP 47 ClockGeneration.Mono47 CG MP 48 ClockGeneration.Mono48 CG MP 49 ClockGeneration.Mono49 CG MP 50 ClockGeneration.Mono50 CG MP 51 ClockGeneration.Ferrite0 CG L 10 ClockGeneration.Ferrite1 CG L 11 ClockGeneration.Ferrite2 CG L 12 ClockGeneration.Ferrite3 CG L 13 ClockGeneration.Ferrite4 CG L 14 ClockGeneration.Ferrite5 CG L 15 ClockGeneration.Ferrite6 CG L 16 ClockGeneration.Ferrite7 CG L 17 ClockGeneration.Ferrite8 CG L 18 ClockGeneration.Ferrite9 CG L 19 ClockGeneration.Ferrite10 CG L 20 ClockGeneration.Ferrite11 CG L 21 ClockGeneration.Ferrite12 CG L 22 ClockGeneration.Ferrite13 CG L 23 ClockGeneration.Ferrite14 CG L 24 ClockGeneration.Ferrite15 CG L 25 ClockGeneration.Ferrite16 CG L 26 ClockGeneration.AVCC_CDC0 CG K 27 ClockGeneration.AVCC_CDC1 CG K 28 ClockGeneration.AVCC_CDC2 CG K 29 ClockGeneration.AVCC_CDC3 CG K 30 ClockGeneration.AVCC_CDC4 CG K 31 ClockGeneration.AVCC_CDC5 CG K 32 ClockGeneration.AVCC_CDC6 CG K 33 ClockGeneration.AVCC_CDC7 CG K 34 ClockGeneration.AVCC_CDC8 CG K 35 ClockGeneration.AVCC_CDC9 CG K 36 ClockGeneration.AVCC_CDC10 CG K 37 ClockGeneration.AVCC_CDC11 CG K 38 ClockGeneration.AVCC_CDC12 CG K 39 ClockGeneration.AVCC_CDC13 CG K 40 ClockGeneration.AVCC_CDC14 CG K 41 ClockGeneration.AVCC_CDC15 CG K 42 ClockGeneration.AVCC_CDC16 CG K 43 ClockGeneration.VC_CDC0 CG K 44 ClockGeneration.VC_CDC1 CG K 45 ClockGeneration.VC_CDC2 CG K 46 ClockGeneration.VC_CDC3 CG K 47 ClockGeneration.VC_CDC4 CG K 48 ClockGeneration.VC_CDC5 CG K 49 ClockGeneration.VC_CDC6 CG K 50 ClockGeneration.VC_CDC7 CG K 51 ClockGeneration.VC_CDC8 CG K 52 ClockGeneration.VC_CDC9 CG K 53 ClockGeneration.VC_CDC10 CG K 54 ClockGeneration.VC_CDC11 CG K 55 ClockGeneration.VC_CDC12 CG K 56 ClockGeneration.VC_CDC13 CG K 57 ClockGeneration.VC_CDC14 CG K 58 ClockGeneration.VC_CDC15 CG K 59 ClockGeneration.VC_CDC16 CG K 60 ClockGeneration.VC_CDC17 CG K 61 ClockGeneration.VC_CDC18 CG K 62 ClockGeneration.VC_CDC19 CG K 63 ClockGeneration.VC_CDC20 CG K 64 ClockGeneration.VC_CDC21 CG K 65 ClockGeneration.VC_CDC22 CG K 66 ClockGeneration.VC_CDC23 CG K 67 ClockGeneration.VC_CDC24 CG K 68 ClockGeneration.VC_CDC25 CG K 69 ClockGeneration.VC_CDC26 CG K 70 ClockGeneration.VC_CDC27 CG K 71 ClockGeneration.VC_CDC28 CG K 72 ClockGeneration.VC_CDC29 CG K 73 ClockGeneration.VC_CDC30 CG K 74 ClockGeneration.VC_CDC31 CG K 75 ClockGeneration.VC_CDC32 CG K 76 ClockGeneration.VC_CDC33 CG K 77 ClockGeneration.VC_CDC34 CG K 78 ClockGeneration.VC_CDC35 CG K 79 ClockGeneration.VC_CDC36 CG K 80 ClockGeneration.VC_CDC37 CG K 81 ClockGeneration.VC_CDC38 CG K 82 ClockGeneration.VC_CDC39 CG K 83 ClockGeneration.VC_CDC40 CG K 84 ClockGeneration.VC_CDC41 CG K 85 ClockGeneration.VC_CDC42 CG K 86 ClockGeneration.VC_CDC43 CG K 87 ClockGeneration.VC_CDC44 CG K 88 ClockGeneration.VC_CDC45 CG K 89 ClockGeneration.VC_CDC46 CG K 90 ClockGeneration.VC_CDC47 CG K 91 ClockGeneration.VC_CDC48 CG K 92 ClockGeneration.VC_CDC49 CG K 93 ClockGeneration.VC_CDC50 CG K 94 ClockGeneration.VC_CDC51 CG K 95 ClockGeneration.VC_CDC52 CG K 96 ClockGeneration.VC_CDC53 CG K 97 ClockGeneration.VC_CDC54 CG K 98 ClockGeneration.VC_CDC55 CG K 99 ClockGeneration.VC_CDC56 CG K 100 ClockGeneration.VC_CDC57 CG K 101 ClockGeneration.VC_CDC58 CG K 102 ClockGeneration.VC_CDC59 CG K 103 ClockGeneration.VC_CDC60 CG K 104 ClockGeneration.VC_CDC61 CG K 105 ClockGeneration.VC_CDC62 CG K 106 ClockGeneration.VC_CDC63 CG K 107 ClockGeneration.VC_CDC64 CG K 108 ClockGeneration.VC_CDC65 CG K 109 ClockGeneration.VC_CDC66 CG K 110 ClockGeneration.VC_CDC67 CG K 111 ClockGeneration.VC_CDC68 CG K 112 ClockGeneration.VC_CDC69 CG K 113 ClockGeneration.VC_CDC70 CG K 114 ClockGeneration.VC_CDC71 CG K 115 ClockGeneration.VC_TDC0 CG T 3 ClockGeneration.VC_TDC1 CG T 4 ClockGeneration.VC_TDC2 CG T 5 ClockGeneration.OSC_CDC0 CG K 116 ClockGeneration.OSC_CDC1 CG K 117 ClockGeneration.OSC_CDC2 CG K 118 DataExchange.DXF_FPGA_A.Fpga.Fpga DX U 1 DataExchange.DXF_FPGA_A.Fpga.INIT_Pullup DX R 1 DataExchange.DXF_FPGA_A.Fpga.VC_CDC0 DX K 1 DataExchange.DXF_FPGA_A.Fpga.VC_CDC1 DX K 2 DataExchange.DXF_FPGA_A.Fpga.VC_CDC2 DX K 3 DataExchange.DXF_FPGA_A.Fpga.VC_CDC3 DX K 4 DataExchange.DXF_FPGA_A.Fpga.VC_CDC4 DX K 5 DataExchange.DXF_FPGA_A.Fpga.VC_CDC5 DX K 6 DataExchange.DXF_FPGA_A.Fpga.VC_CDC6 DX K 7 DataExchange.DXF_FPGA_A.Fpga.VC_CDC7 DX K 8 DataExchange.DXF_FPGA_A.Fpga.VB_CDC0 DX K 9 DataExchange.DXF_FPGA_A.Fpga.VB_CDC1 DX K 10 DataExchange.DXF_FPGA_A.Fpga.VB_CDC2 DX K 11 DataExchange.DXF_FPGA_A.Fpga.VB_CDC3 DX K 12 DataExchange.DXF_FPGA_A.Fpga.VB_CDC4 DX K 13 DataExchange.DXF_FPGA_A.Fpga.VB_CDC5 DX K 14 DataExchange.DXF_FPGA_A.Fpga.VB_CDC6 DX K 15 DataExchange.DXF_FPGA_A.Fpga.VB_CDC7 DX K 16 DataExchange.DXF_FPGA_A.Fpga.VC_TDC0 DX T 1 DataExchange.DXF_FPGA_A.Fpga.VB_TDC0 DX T 2 DataExchange.DXF_FPGA_B.Fpga.Fpga DX U 2 DataExchange.DXF_FPGA_B.Fpga.INIT_Pullup DX R 2 DataExchange.DXF_FPGA_B.Fpga.VC_CDC0 DX K 17 DataExchange.DXF_FPGA_B.Fpga.VC_CDC1 DX K 18 DataExchange.DXF_FPGA_B.Fpga.VC_CDC2 DX K 19 DataExchange.DXF_FPGA_B.Fpga.VC_CDC3 DX K 20 DataExchange.DXF_FPGA_B.Fpga.VC_CDC4 DX K 21 DataExchange.DXF_FPGA_B.Fpga.VC_CDC5 DX K 22 DataExchange.DXF_FPGA_B.Fpga.VC_CDC6 DX K 23 DataExchange.DXF_FPGA_B.Fpga.VC_CDC7 DX K 24 DataExchange.DXF_FPGA_B.Fpga.VB_CDC0 DX K 25 DataExchange.DXF_FPGA_B.Fpga.VB_CDC1 DX K 26 DataExchange.DXF_FPGA_B.Fpga.VB_CDC2 DX K 27 DataExchange.DXF_FPGA_B.Fpga.VB_CDC3 DX K 28 DataExchange.DXF_FPGA_B.Fpga.VB_CDC4 DX K 29 DataExchange.DXF_FPGA_B.Fpga.VB_CDC5 DX K 30 DataExchange.DXF_FPGA_B.Fpga.VB_CDC6 DX K 31 DataExchange.DXF_FPGA_B.Fpga.VB_CDC7 DX K 32 DataExchange.DXF_FPGA_B.Fpga.VC_TDC0 DX T 3 DataExchange.DXF_FPGA_B.Fpga.VB_TDC0 DX T 4 DataExchange.DXB_FPGA.Fpga.Fpga DX U 3 DataExchange.DXB_FPGA.Fpga.INIT_Pullup DX R 3 DataExchange.DXB_FPGA.Fpga.VC_CDC0 DX K 33 DataExchange.DXB_FPGA.Fpga.VC_CDC1 DX K 34 DataExchange.DXB_FPGA.Fpga.VC_CDC2 DX K 35 DataExchange.DXB_FPGA.Fpga.VC_CDC3 DX K 36 DataExchange.DXB_FPGA.Fpga.VC_CDC4 DX K 37 DataExchange.DXB_FPGA.Fpga.VC_CDC5 DX K 38 DataExchange.DXB_FPGA.Fpga.VC_CDC6 DX K 39 DataExchange.DXB_FPGA.Fpga.VC_CDC7 DX K 40 DataExchange.DXB_FPGA.Fpga.VB_CDC0 DX K 41 DataExchange.DXB_FPGA.Fpga.VB_CDC1 DX K 42 DataExchange.DXB_FPGA.Fpga.VB_CDC2 DX K 43 DataExchange.DXB_FPGA.Fpga.VB_CDC3 DX K 44 DataExchange.DXB_FPGA.Fpga.VB_CDC4 DX K 45 DataExchange.DXB_FPGA.Fpga.VB_CDC5 DX K 46 DataExchange.DXB_FPGA.Fpga.VB_CDC6 DX K 47 DataExchange.DXB_FPGA.Fpga.VB_CDC7 DX K 48 DataExchange.DXB_FPGA.Fpga.VC_TDC0 DX T 5 DataExchange.DXB_FPGA.Fpga.VB_TDC0 DX T 6 DataExchange.HostFIFO.Fifo DX U 4 DataExchange.HostFIFO.VC_CDC0 DX K 49 DataExchange.HostFIFO.VC_CDC1 DX K 50 DataExchange.HostFIFO.VC_CDC2 DX K 51 DataExchange.HostFIFO.VC_CDC3 DX K 52 DataExchange.HostFIFO.VC_CDC4 DX K 53 DataExchange.HostFIFO.VC_CDC5 DX K 54 DataExchange.HostFIFO.VC_CDC6 DX K 55 DataExchange.HostFIFO.VC_CDC7 DX K 56 DataExchange.HostFIFO.VC_CDC8 DX K 57 DataExchange.HostFIFO.VC_CDC9 DX K 58 DataExchange.HostFIFO.VC_CDC10 DX K 59 DataExchange.HostFIFO.VC_TDC0 DX T 7 DataExchange.PullupDXF_HG0 DX R 4 DataExchange.PullupDXF_HG1 DX R 5 DataExchange.PullupDXF_HG2 DX R 6 DataExchange.PullupDXF_HG3 DX R 7 DataExchange.PullupDXC_A9 DX R 8 DataExchange.PullupDXC_A8 DX R 9 DataExchange.PullupDXC_A7 DX R 10 DataExchange.PullupDXC_A6 DX R 11 DataExchange.PullupDXC_B9 DX R 12 DataExchange.PullupDXC_B8 DX R 13 DataExchange.PullupDXC_B7 DX R 14 DataExchange.PullupDXC_B6 DX R 15 DataExchange.PullupMRS DX R 16 DataExchange.PullupWEN DX R 17 DataExchange.PullupLD DX R 18 DPU_Control.DC_FPGA.Fpga.Fpga DC U 1 DPU_Control.DC_FPGA.Fpga.INIT_Pullup DC R 1 DPU_Control.DC_FPGA.Fpga.VC_CDC0 DC K 1 DPU_Control.DC_FPGA.Fpga.VC_CDC1 DC K 2 DPU_Control.DC_FPGA.Fpga.VC_CDC2 DC K 3 DPU_Control.DC_FPGA.Fpga.VC_CDC3 DC K 4 DPU_Control.DC_FPGA.Fpga.VC_CDC4 DC K 5 DPU_Control.DC_FPGA.Fpga.VC_CDC5 DC K 6 DPU_Control.DC_FPGA.Fpga.VC_CDC6 DC K 7 DPU_Control.DC_FPGA.Fpga.VC_CDC7 DC K 8 DPU_Control.DC_FPGA.Fpga.VB_CDC0 DC K 9 DPU_Control.DC_FPGA.Fpga.VB_CDC1 DC K 10 DPU_Control.DC_FPGA.Fpga.VB_CDC2 DC K 11 DPU_Control.DC_FPGA.Fpga.VB_CDC3 DC K 12 DPU_Control.DC_FPGA.Fpga.VB_CDC4 DC K 13 DPU_Control.DC_FPGA.Fpga.VB_CDC5 DC K 14 DPU_Control.DC_FPGA.Fpga.VB_CDC6 DC K 15 DPU_Control.DC_FPGA.Fpga.VB_CDC7 DC K 16 DPU_Control.DC_FPGA.Fpga.VC_TDC0 DC T 1 DPU_Control.DC_FPGA.Fpga.VB_TDC0 DC T 2 DPU_Control.PullupDCC_A10 DC R 2 DPU_Control.PullupDCC_A9 DC R 3 DPU_Control.PullupDCC_B10 DC R 4 DPU_Control.PullupDCC_B9 DC R 5 FrontPanel.EmuHeader FP H 1 FrontPanel.JTAG_Header FP H 2 FrontPanel.TTC_Header FP H 3 FrontPanel.Switch_JT_CG FP SW 1 FrontPanel.ESD_Strip FP S 1 FrontPanel.ESD_Res0 FP R 1 FrontPanel.ESD_Res1 FP R 2 FrontPanel.ESD_Res2 FP R 3 FrontPanel.ESD_Res3 FP R 4 FrontPanel.PanelHoles0 FP M 1 FrontPanel.PanelHoles1 FP M 2 FrontPanel.PanelHoles2 FP M 3 FrontPanel.PanelHoles3 FP M 4 FrontPanel.Switches0 FP SW 2 FrontPanel.Switches1 FP SW 3 FrontPanel.Switches2 FP SW 4 FrontPanel.LEDpwrVC FP D 1 FrontPanel.LEDpwrVB FP D 2 FrontPanel.LEDpwrVA5 FP D 3 FrontPanel.LEDhpu FP D 4 FrontPanel.LEDvme FP D 5 FrontPanel.Rled0 FP R 5 FrontPanel.Rled1 FP R 6 FrontPanel.Rled2 FP R 7 FrontPanel.Rled3 FP R 8 FrontPanel.Rled4 FP R 9 FrontPanel.Rled5 FP R 10 FrontPanel.Rled6 FP R 11 FrontPanel.Rled7 FP R 12 FrontPanel.Rled8 FP R 13 FrontPanel.Rled9 FP R 14 FrontPanel.Rled10 FP R 15 FrontPanel.Rgnd FP R 16 Half_A.DPU0.Conn A0 GP 1 Half_A.DPU0.SwitchEMU A0 U 1 Half_A.DPU0.PulldownPRESENT A0 R 1 Half_A.DPU0.PullupFINIT_N A0 R 2 Half_A.DPU0.PullupEFINIT_N A0 R 3 Half_A.DPU0.PullupVREF A0 R 4 Half_A.DPU0.PulldownVREF A0 R 5 Half_A.DPU0.VC_CDC0 A0 K 1 Half_A.DPU0.VC_CDC1 A0 K 2 Half_A.DPU0.VC_CDC2 A0 K 3 Half_A.DPU0.VC_CDC3 A0 K 4 Half_A.DPU0.VB_CDC0 A0 K 5 Half_A.DPU0.VB_CDC1 A0 K 6 Half_A.DPU0.VB_CDC2 A0 K 7 Half_A.DPU0.VB_CDC3 A0 K 8 Half_A.DPU0.VA_CDC0 A0 K 9 Half_A.DPU0.VA_CDC1 A0 K 10 Half_A.DPU0.VA_CDC2 A0 K 11 Half_A.DPU0.VA_CDC3 A0 K 12 Half_A.DPU0.VC_TDC0 A0 T 1 Half_A.DPU0.VB_TDC0 A0 T 2 Half_A.DPU0.VA_TDC0 A0 T 3 Half_A.DPU0.PulldownRESET_N A0 R 6 Half_A.DPU1.Conn A1 GP 1 Half_A.DPU1.SwitchEMU A1 U 1 Half_A.DPU1.PulldownPRESENT A1 R 1 Half_A.DPU1.PullupFINIT_N A1 R 2 Half_A.DPU1.PullupEFINIT_N A1 R 3 Half_A.DPU1.PullupVREF A1 R 4 Half_A.DPU1.PulldownVREF A1 R 5 Half_A.DPU1.VC_CDC0 A1 K 1 Half_A.DPU1.VC_CDC1 A1 K 2 Half_A.DPU1.VC_CDC2 A1 K 3 Half_A.DPU1.VC_CDC3 A1 K 4 Half_A.DPU1.VB_CDC0 A1 K 5 Half_A.DPU1.VB_CDC1 A1 K 6 Half_A.DPU1.VB_CDC2 A1 K 7 Half_A.DPU1.VB_CDC3 A1 K 8 Half_A.DPU1.VA_CDC0 A1 K 9 Half_A.DPU1.VA_CDC1 A1 K 10 Half_A.DPU1.VA_CDC2 A1 K 11 Half_A.DPU1.VA_CDC3 A1 K 12 Half_A.DPU1.VC_TDC0 A1 T 1 Half_A.DPU1.VB_TDC0 A1 T 2 Half_A.DPU1.VA_TDC0 A1 T 3 Half_A.DPU1.PulldownRESET_N A1 R 6 Half_A.DPU2.Conn A2 GP 1 Half_A.DPU2.SwitchEMU A2 U 1 Half_A.DPU2.PulldownPRESENT A2 R 1 Half_A.DPU2.PullupFINIT_N A2 R 2 Half_A.DPU2.PullupEFINIT_N A2 R 3 Half_A.DPU2.PullupVREF A2 R 4 Half_A.DPU2.PulldownVREF A2 R 5 Half_A.DPU2.VC_CDC0 A2 K 1 Half_A.DPU2.VC_CDC1 A2 K 2 Half_A.DPU2.VC_CDC2 A2 K 3 Half_A.DPU2.VC_CDC3 A2 K 4 Half_A.DPU2.VB_CDC0 A2 K 5 Half_A.DPU2.VB_CDC1 A2 K 6 Half_A.DPU2.VB_CDC2 A2 K 7 Half_A.DPU2.VB_CDC3 A2 K 8 Half_A.DPU2.VA_CDC0 A2 K 9 Half_A.DPU2.VA_CDC1 A2 K 10 Half_A.DPU2.VA_CDC2 A2 K 11 Half_A.DPU2.VA_CDC3 A2 K 12 Half_A.DPU2.VC_TDC0 A2 T 1 Half_A.DPU2.VB_TDC0 A2 T 2 Half_A.DPU2.VA_TDC0 A2 T 3 Half_A.DPU2.PulldownRESET_N A2 R 6 Half_A.DPU3.Conn A3 GP 1 Half_A.DPU3.SwitchEMU A3 U 1 Half_A.DPU3.PulldownPRESENT A3 R 1 Half_A.DPU3.PullupFINIT_N A3 R 2 Half_A.DPU3.PullupEFINIT_N A3 R 3 Half_A.DPU3.PullupVREF A3 R 4 Half_A.DPU3.PulldownVREF A3 R 5 Half_A.DPU3.VC_CDC0 A3 K 1 Half_A.DPU3.VC_CDC1 A3 K 2 Half_A.DPU3.VC_CDC2 A3 K 3 Half_A.DPU3.VC_CDC3 A3 K 4 Half_A.DPU3.VB_CDC0 A3 K 5 Half_A.DPU3.VB_CDC1 A3 K 6 Half_A.DPU3.VB_CDC2 A3 K 7 Half_A.DPU3.VB_CDC3 A3 K 8 Half_A.DPU3.VA_CDC0 A3 K 9 Half_A.DPU3.VA_CDC1 A3 K 10 Half_A.DPU3.VA_CDC2 A3 K 11 Half_A.DPU3.VA_CDC3 A3 K 12 Half_A.DPU3.VC_TDC0 A3 T 1 Half_A.DPU3.VB_TDC0 A3 T 2 Half_A.DPU3.VA_TDC0 A3 T 3 Half_A.DPU3.PulldownRESET_N A3 R 6 Half_A.DPU4.Conn A4 GP 1 Half_A.DPU4.SwitchEMU A4 U 1 Half_A.DPU4.PulldownPRESENT A4 R 1 Half_A.DPU4.PullupFINIT_N A4 R 2 Half_A.DPU4.PullupEFINIT_N A4 R 3 Half_A.DPU4.PullupVREF A4 R 4 Half_A.DPU4.PulldownVREF A4 R 5 Half_A.DPU4.VC_CDC0 A4 K 1 Half_A.DPU4.VC_CDC1 A4 K 2 Half_A.DPU4.VC_CDC2 A4 K 3 Half_A.DPU4.VC_CDC3 A4 K 4 Half_A.DPU4.VB_CDC0 A4 K 5 Half_A.DPU4.VB_CDC1 A4 K 6 Half_A.DPU4.VB_CDC2 A4 K 7 Half_A.DPU4.VB_CDC3 A4 K 8 Half_A.DPU4.VA_CDC0 A4 K 9 Half_A.DPU4.VA_CDC1 A4 K 10 Half_A.DPU4.VA_CDC2 A4 K 11 Half_A.DPU4.VA_CDC3 A4 K 12 Half_A.DPU4.VC_TDC0 A4 T 1 Half_A.DPU4.VB_TDC0 A4 T 2 Half_A.DPU4.VA_TDC0 A4 T 3 Half_A.DPU4.PulldownRESET_N A4 R 6 Half_A.DPU5.Conn A5 GP 1 Half_A.DPU5.SwitchEMU A5 U 1 Half_A.DPU5.PulldownPRESENT A5 R 1 Half_A.DPU5.PullupFINIT_N A5 R 2 Half_A.DPU5.PullupEFINIT_N A5 R 3 Half_A.DPU5.PullupVREF A5 R 4 Half_A.DPU5.PulldownVREF A5 R 5 Half_A.DPU5.VC_CDC0 A5 K 1 Half_A.DPU5.VC_CDC1 A5 K 2 Half_A.DPU5.VC_CDC2 A5 K 3 Half_A.DPU5.VC_CDC3 A5 K 4 Half_A.DPU5.VB_CDC0 A5 K 5 Half_A.DPU5.VB_CDC1 A5 K 6 Half_A.DPU5.VB_CDC2 A5 K 7 Half_A.DPU5.VB_CDC3 A5 K 8 Half_A.DPU5.VA_CDC0 A5 K 9 Half_A.DPU5.VA_CDC1 A5 K 10 Half_A.DPU5.VA_CDC2 A5 K 11 Half_A.DPU5.VA_CDC3 A5 K 12 Half_A.DPU5.VC_TDC0 A5 T 1 Half_A.DPU5.VB_TDC0 A5 T 2 Half_A.DPU5.VA_TDC0 A5 T 3 Half_A.DPU5.PulldownRESET_N A5 R 6 Half_A.VC_TDC0 A T 1 Half_A.VB_TDC0 A T 2 Half_A.VA_TDC0 A T 3 Half_B.DPU0.Conn B0 GP 1 Half_B.DPU0.SwitchEMU B0 U 1 Half_B.DPU0.PulldownPRESENT B0 R 1 Half_B.DPU0.PullupFINIT_N B0 R 2 Half_B.DPU0.PullupEFINIT_N B0 R 3 Half_B.DPU0.PullupVREF B0 R 4 Half_B.DPU0.PulldownVREF B0 R 5 Half_B.DPU0.VC_CDC0 B0 K 1 Half_B.DPU0.VC_CDC1 B0 K 2 Half_B.DPU0.VC_CDC2 B0 K 3 Half_B.DPU0.VC_CDC3 B0 K 4 Half_B.DPU0.VB_CDC0 B0 K 5 Half_B.DPU0.VB_CDC1 B0 K 6 Half_B.DPU0.VB_CDC2 B0 K 7 Half_B.DPU0.VB_CDC3 B0 K 8 Half_B.DPU0.VA_CDC0 B0 K 9 Half_B.DPU0.VA_CDC1 B0 K 10 Half_B.DPU0.VA_CDC2 B0 K 11 Half_B.DPU0.VA_CDC3 B0 K 12 Half_B.DPU0.VC_TDC0 B0 T 1 Half_B.DPU0.VB_TDC0 B0 T 2 Half_B.DPU0.VA_TDC0 B0 T 3 Half_B.DPU0.PulldownRESET_N B0 R 6 Half_B.DPU1.Conn B1 GP 1 Half_B.DPU1.SwitchEMU B1 U 1 Half_B.DPU1.PulldownPRESENT B1 R 1 Half_B.DPU1.PullupFINIT_N B1 R 2 Half_B.DPU1.PullupEFINIT_N B1 R 3 Half_B.DPU1.PullupVREF B1 R 4 Half_B.DPU1.PulldownVREF B1 R 5 Half_B.DPU1.VC_CDC0 B1 K 1 Half_B.DPU1.VC_CDC1 B1 K 2 Half_B.DPU1.VC_CDC2 B1 K 3 Half_B.DPU1.VC_CDC3 B1 K 4 Half_B.DPU1.VB_CDC0 B1 K 5 Half_B.DPU1.VB_CDC1 B1 K 6 Half_B.DPU1.VB_CDC2 B1 K 7 Half_B.DPU1.VB_CDC3 B1 K 8 Half_B.DPU1.VA_CDC0 B1 K 9 Half_B.DPU1.VA_CDC1 B1 K 10 Half_B.DPU1.VA_CDC2 B1 K 11 Half_B.DPU1.VA_CDC3 B1 K 12 Half_B.DPU1.VC_TDC0 B1 T 1 Half_B.DPU1.VB_TDC0 B1 T 2 Half_B.DPU1.VA_TDC0 B1 T 3 Half_B.DPU1.PulldownRESET_N B1 R 6 Half_B.DPU2.Conn B2 GP 1 Half_B.DPU2.SwitchEMU B2 U 1 Half_B.DPU2.PulldownPRESENT B2 R 1 Half_B.DPU2.PullupFINIT_N B2 R 2 Half_B.DPU2.PullupEFINIT_N B2 R 3 Half_B.DPU2.PullupVREF B2 R 4 Half_B.DPU2.PulldownVREF B2 R 5 Half_B.DPU2.VC_CDC0 B2 K 1 Half_B.DPU2.VC_CDC1 B2 K 2 Half_B.DPU2.VC_CDC2 B2 K 3 Half_B.DPU2.VC_CDC3 B2 K 4 Half_B.DPU2.VB_CDC0 B2 K 5 Half_B.DPU2.VB_CDC1 B2 K 6 Half_B.DPU2.VB_CDC2 B2 K 7 Half_B.DPU2.VB_CDC3 B2 K 8 Half_B.DPU2.VA_CDC0 B2 K 9 Half_B.DPU2.VA_CDC1 B2 K 10 Half_B.DPU2.VA_CDC2 B2 K 11 Half_B.DPU2.VA_CDC3 B2 K 12 Half_B.DPU2.VC_TDC0 B2 T 1 Half_B.DPU2.VB_TDC0 B2 T 2 Half_B.DPU2.VA_TDC0 B2 T 3 Half_B.DPU2.PulldownRESET_N B2 R 6 Half_B.DPU3.Conn B3 GP 1 Half_B.DPU3.SwitchEMU B3 U 1 Half_B.DPU3.PulldownPRESENT B3 R 1 Half_B.DPU3.PullupFINIT_N B3 R 2 Half_B.DPU3.PullupEFINIT_N B3 R 3 Half_B.DPU3.PullupVREF B3 R 4 Half_B.DPU3.PulldownVREF B3 R 5 Half_B.DPU3.VC_CDC0 B3 K 1 Half_B.DPU3.VC_CDC1 B3 K 2 Half_B.DPU3.VC_CDC2 B3 K 3 Half_B.DPU3.VC_CDC3 B3 K 4 Half_B.DPU3.VB_CDC0 B3 K 5 Half_B.DPU3.VB_CDC1 B3 K 6 Half_B.DPU3.VB_CDC2 B3 K 7 Half_B.DPU3.VB_CDC3 B3 K 8 Half_B.DPU3.VA_CDC0 B3 K 9 Half_B.DPU3.VA_CDC1 B3 K 10 Half_B.DPU3.VA_CDC2 B3 K 11 Half_B.DPU3.VA_CDC3 B3 K 12 Half_B.DPU3.VC_TDC0 B3 T 1 Half_B.DPU3.VB_TDC0 B3 T 2 Half_B.DPU3.VA_TDC0 B3 T 3 Half_B.DPU3.PulldownRESET_N B3 R 6 Half_B.DPU4.Conn B4 GP 1 Half_B.DPU4.SwitchEMU B4 U 1 Half_B.DPU4.PulldownPRESENT B4 R 1 Half_B.DPU4.PullupFINIT_N B4 R 2 Half_B.DPU4.PullupEFINIT_N B4 R 3 Half_B.DPU4.PullupVREF B4 R 4 Half_B.DPU4.PulldownVREF B4 R 5 Half_B.DPU4.VC_CDC0 B4 K 1 Half_B.DPU4.VC_CDC1 B4 K 2 Half_B.DPU4.VC_CDC2 B4 K 3 Half_B.DPU4.VC_CDC3 B4 K 4 Half_B.DPU4.VB_CDC0 B4 K 5 Half_B.DPU4.VB_CDC1 B4 K 6 Half_B.DPU4.VB_CDC2 B4 K 7 Half_B.DPU4.VB_CDC3 B4 K 8 Half_B.DPU4.VA_CDC0 B4 K 9 Half_B.DPU4.VA_CDC1 B4 K 10 Half_B.DPU4.VA_CDC2 B4 K 11 Half_B.DPU4.VA_CDC3 B4 K 12 Half_B.DPU4.VC_TDC0 B4 T 1 Half_B.DPU4.VB_TDC0 B4 T 2 Half_B.DPU4.VA_TDC0 B4 T 3 Half_B.DPU4.PulldownRESET_N B4 R 6 Half_B.DPU5.Conn B5 GP 1 Half_B.DPU5.SwitchEMU B5 U 1 Half_B.DPU5.PulldownPRESENT B5 R 1 Half_B.DPU5.PullupFINIT_N B5 R 2 Half_B.DPU5.PullupEFINIT_N B5 R 3 Half_B.DPU5.PullupVREF B5 R 4 Half_B.DPU5.PulldownVREF B5 R 5 Half_B.DPU5.VC_CDC0 B5 K 1 Half_B.DPU5.VC_CDC1 B5 K 2 Half_B.DPU5.VC_CDC2 B5 K 3 Half_B.DPU5.VC_CDC3 B5 K 4 Half_B.DPU5.VB_CDC0 B5 K 5 Half_B.DPU5.VB_CDC1 B5 K 6 Half_B.DPU5.VB_CDC2 B5 K 7 Half_B.DPU5.VB_CDC3 B5 K 8 Half_B.DPU5.VA_CDC0 B5 K 9 Half_B.DPU5.VA_CDC1 B5 K 10 Half_B.DPU5.VA_CDC2 B5 K 11 Half_B.DPU5.VA_CDC3 B5 K 12 Half_B.DPU5.VC_TDC0 B5 T 1 Half_B.DPU5.VB_TDC0 B5 T 2 Half_B.DPU5.VA_TDC0 B5 T 3 Half_B.DPU5.PulldownRESET_N B5 R 6 Half_B.VC_TDC0 B T 1 Half_B.VB_TDC0 B T 2 Half_B.VA_TDC0 B T 3 Host.HPU.Conn HO GP 1 Host.HPU.SwitchEMU HO U 1 Host.HPU.PulldownPRESENT HO R 1 Host.HPU.PullupFINIT_N HO R 2 Host.HPU.PullupEFINIT_N HO R 3 Host.HPU.PullupVREF HO R 4 Host.HPU.PulldownVREF HO R 5 Host.HPU.VC_CDC0 HO K 1 Host.HPU.VC_CDC1 HO K 2 Host.HPU.VC_CDC2 HO K 3 Host.HPU.VC_CDC3 HO K 4 Host.HPU.VB_CDC0 HO K 5 Host.HPU.VB_CDC1 HO K 6 Host.HPU.VB_CDC2 HO K 7 Host.HPU.VB_CDC3 HO K 8 Host.HPU.VA_CDC0 HO K 9 Host.HPU.VA_CDC1 HO K 10 Host.HPU.VA_CDC2 HO K 11 Host.HPU.VA_CDC3 HO K 12 Host.HPU.VC_TDC0 HO T 1 Host.HPU.VB_TDC0 HO T 2 Host.HPU.VA_TDC0 HO T 3 Host.HPU.PullupRESET_N HO R 6 Host.SwitchJTAG HO U 2 Host.HOST_PLD.Cpld HO U 3 Host.BDF_XCVR_LOW HO U 4 Host.BDF_XCVR_HIGH HO U 5 Host.BDG_XCVR HO U 6 Host.BDH_XCVR_LOW HO U 7 Host.BDH_XCVR_HIGH HO U 8 Host.SerialNumber HO U 9 Host.PullupSN HO R 7 Host.Term_VFIFO_WR_CLK HO R 8 Host.Term_HFIFO_RD_CLK HO R 9 Host.Term_DPRAM_WE_N HO R 10 Host.Term_HFL_WE_N HO R 11 Host.Term_DS1 HO RP 1 Host.Term_DS2 HO RP 2 Host.VCC_CDC0 HO K 13 Host.VCC_CDC1 HO K 14 Host.VCC_CDC2 HO K 15 Host.VCC_CDC3 HO K 16 Host.VCC_CDC4 HO K 17 Host.VCC_CDC5 HO K 18 Host.VCC_CDC6 HO K 19 Host.VCC_CDC7 HO K 20 Host.VCC_CDC8 HO K 21 Host.VCC_CDC9 HO K 22 Host.VCC_CDC10 HO K 23 Host.VCC_CDC11 HO K 24 Host.VCC_CDC12 HO K 25 Host.VCC_CDC13 HO K 26 Host.VCC_CDC14 HO K 27 Host.VCC_CDC15 HO K 28 Host.VCC_CDC16 HO K 29 Host.VCC_CDC17 HO K 30 Host.VCC_CDC18 HO K 31 Host.VCC_CDC19 HO K 32 Host.VCC_CDC20 HO K 33 Host.VCC_CDC21 HO K 34 Host.VCC_CDC22 HO K 35 Host.VCC_CDC23 HO K 36 Host.VCC_TDC0 HO T 4 Host.VCC_TDC1 HO T 5 Host.VCC_TDC2 HO T 6 Interconnect.BPI_FPGA0.Fpga.Fpga IC U 1 Interconnect.BPI_FPGA0.Fpga.INIT_Pullup IC R 1 Interconnect.BPI_FPGA0.Fpga.VC_CDC0 IC K 1 Interconnect.BPI_FPGA0.Fpga.VC_CDC1 IC K 2 Interconnect.BPI_FPGA0.Fpga.VC_CDC2 IC K 3 Interconnect.BPI_FPGA0.Fpga.VC_CDC3 IC K 4 Interconnect.BPI_FPGA0.Fpga.VC_CDC4 IC K 5 Interconnect.BPI_FPGA0.Fpga.VC_CDC5 IC K 6 Interconnect.BPI_FPGA0.Fpga.VC_CDC6 IC K 7 Interconnect.BPI_FPGA0.Fpga.VC_CDC7 IC K 8 Interconnect.BPI_FPGA0.Fpga.VB_CDC0 IC K 9 Interconnect.BPI_FPGA0.Fpga.VB_CDC1 IC K 10 Interconnect.BPI_FPGA0.Fpga.VB_CDC2 IC K 11 Interconnect.BPI_FPGA0.Fpga.VB_CDC3 IC K 12 Interconnect.BPI_FPGA0.Fpga.VB_CDC4 IC K 13 Interconnect.BPI_FPGA0.Fpga.VB_CDC5 IC K 14 Interconnect.BPI_FPGA0.Fpga.VB_CDC6 IC K 15 Interconnect.BPI_FPGA0.Fpga.VB_CDC7 IC K 16 Interconnect.BPI_FPGA0.Fpga.VC_TDC0 IC T 1 Interconnect.BPI_FPGA0.Fpga.VB_TDC0 IC T 2 Interconnect.BPI_FPGA0.Fpga.PullupVREF IC R 2 Interconnect.BPI_FPGA0.Fpga.PulldownVREF IC R 3 Interconnect.BPI_FPGA0.Fpga.VREF_CDC IC K 17 Interconnect.BPI_FPGA1.Fpga.Fpga IC U 2 Interconnect.BPI_FPGA1.Fpga.INIT_Pullup IC R 4 Interconnect.BPI_FPGA1.Fpga.VC_CDC0 IC K 18 Interconnect.BPI_FPGA1.Fpga.VC_CDC1 IC K 19 Interconnect.BPI_FPGA1.Fpga.VC_CDC2 IC K 20 Interconnect.BPI_FPGA1.Fpga.VC_CDC3 IC K 21 Interconnect.BPI_FPGA1.Fpga.VC_CDC4 IC K 22 Interconnect.BPI_FPGA1.Fpga.VC_CDC5 IC K 23 Interconnect.BPI_FPGA1.Fpga.VC_CDC6 IC K 24 Interconnect.BPI_FPGA1.Fpga.VC_CDC7 IC K 25 Interconnect.BPI_FPGA1.Fpga.VB_CDC0 IC K 26 Interconnect.BPI_FPGA1.Fpga.VB_CDC1 IC K 27 Interconnect.BPI_FPGA1.Fpga.VB_CDC2 IC K 28 Interconnect.BPI_FPGA1.Fpga.VB_CDC3 IC K 29 Interconnect.BPI_FPGA1.Fpga.VB_CDC4 IC K 30 Interconnect.BPI_FPGA1.Fpga.VB_CDC5 IC K 31 Interconnect.BPI_FPGA1.Fpga.VB_CDC6 IC K 32 Interconnect.BPI_FPGA1.Fpga.VB_CDC7 IC K 33 Interconnect.BPI_FPGA1.Fpga.VC_TDC0 IC T 3 Interconnect.BPI_FPGA1.Fpga.VB_TDC0 IC T 4 Interconnect.BPI_FPGA1.Fpga.PullupVREF IC R 5 Interconnect.BPI_FPGA1.Fpga.PulldownVREF IC R 6 Interconnect.BPI_FPGA1.Fpga.VREF_CDC IC K 34 Interconnect.BPI_FPGA2.Fpga.Fpga IC U 3 Interconnect.BPI_FPGA2.Fpga.INIT_Pullup IC R 7 Interconnect.BPI_FPGA2.Fpga.VC_CDC0 IC K 35 Interconnect.BPI_FPGA2.Fpga.VC_CDC1 IC K 36 Interconnect.BPI_FPGA2.Fpga.VC_CDC2 IC K 37 Interconnect.BPI_FPGA2.Fpga.VC_CDC3 IC K 38 Interconnect.BPI_FPGA2.Fpga.VC_CDC4 IC K 39 Interconnect.BPI_FPGA2.Fpga.VC_CDC5 IC K 40 Interconnect.BPI_FPGA2.Fpga.VC_CDC6 IC K 41 Interconnect.BPI_FPGA2.Fpga.VC_CDC7 IC K 42 Interconnect.BPI_FPGA2.Fpga.VB_CDC0 IC K 43 Interconnect.BPI_FPGA2.Fpga.VB_CDC1 IC K 44 Interconnect.BPI_FPGA2.Fpga.VB_CDC2 IC K 45 Interconnect.BPI_FPGA2.Fpga.VB_CDC3 IC K 46 Interconnect.BPI_FPGA2.Fpga.VB_CDC4 IC K 47 Interconnect.BPI_FPGA2.Fpga.VB_CDC5 IC K 48 Interconnect.BPI_FPGA2.Fpga.VB_CDC6 IC K 49 Interconnect.BPI_FPGA2.Fpga.VB_CDC7 IC K 50 Interconnect.BPI_FPGA2.Fpga.VC_TDC0 IC T 5 Interconnect.BPI_FPGA2.Fpga.VB_TDC0 IC T 6 Interconnect.BPI_FPGA2.Fpga.PullupVREF IC R 8 Interconnect.BPI_FPGA2.Fpga.PulldownVREF IC R 9 Interconnect.BPI_FPGA2.Fpga.VREF_CDC IC K 51 Interconnect.BPI_FPGA3.Fpga.Fpga IC U 4 Interconnect.BPI_FPGA3.Fpga.INIT_Pullup IC R 10 Interconnect.BPI_FPGA3.Fpga.VC_CDC0 IC K 52 Interconnect.BPI_FPGA3.Fpga.VC_CDC1 IC K 53 Interconnect.BPI_FPGA3.Fpga.VC_CDC2 IC K 54 Interconnect.BPI_FPGA3.Fpga.VC_CDC3 IC K 55 Interconnect.BPI_FPGA3.Fpga.VC_CDC4 IC K 56 Interconnect.BPI_FPGA3.Fpga.VC_CDC5 IC K 57 Interconnect.BPI_FPGA3.Fpga.VC_CDC6 IC K 58 Interconnect.BPI_FPGA3.Fpga.VC_CDC7 IC K 59 Interconnect.BPI_FPGA3.Fpga.VB_CDC0 IC K 60 Interconnect.BPI_FPGA3.Fpga.VB_CDC1 IC K 61 Interconnect.BPI_FPGA3.Fpga.VB_CDC2 IC K 62 Interconnect.BPI_FPGA3.Fpga.VB_CDC3 IC K 63 Interconnect.BPI_FPGA3.Fpga.VB_CDC4 IC K 64 Interconnect.BPI_FPGA3.Fpga.VB_CDC5 IC K 65 Interconnect.BPI_FPGA3.Fpga.VB_CDC6 IC K 66 Interconnect.BPI_FPGA3.Fpga.VB_CDC7 IC K 67 Interconnect.BPI_FPGA3.Fpga.VC_TDC0 IC T 7 Interconnect.BPI_FPGA3.Fpga.VB_TDC0 IC T 8 Interconnect.BPI_FPGA3.Fpga.PullupVREF IC R 11 Interconnect.BPI_FPGA3.Fpga.PulldownVREF IC R 12 Interconnect.BPI_FPGA3.Fpga.VREF_CDC IC K 68 Interconnect.BPI_FPGA4.Fpga.Fpga IC U 5 Interconnect.BPI_FPGA4.Fpga.INIT_Pullup IC R 13 Interconnect.BPI_FPGA4.Fpga.VC_CDC0 IC K 69 Interconnect.BPI_FPGA4.Fpga.VC_CDC1 IC K 70 Interconnect.BPI_FPGA4.Fpga.VC_CDC2 IC K 71 Interconnect.BPI_FPGA4.Fpga.VC_CDC3 IC K 72 Interconnect.BPI_FPGA4.Fpga.VC_CDC4 IC K 73 Interconnect.BPI_FPGA4.Fpga.VC_CDC5 IC K 74 Interconnect.BPI_FPGA4.Fpga.VC_CDC6 IC K 75 Interconnect.BPI_FPGA4.Fpga.VC_CDC7 IC K 76 Interconnect.BPI_FPGA4.Fpga.VB_CDC0 IC K 77 Interconnect.BPI_FPGA4.Fpga.VB_CDC1 IC K 78 Interconnect.BPI_FPGA4.Fpga.VB_CDC2 IC K 79 Interconnect.BPI_FPGA4.Fpga.VB_CDC3 IC K 80 Interconnect.BPI_FPGA4.Fpga.VB_CDC4 IC K 81 Interconnect.BPI_FPGA4.Fpga.VB_CDC5 IC K 82 Interconnect.BPI_FPGA4.Fpga.VB_CDC6 IC K 83 Interconnect.BPI_FPGA4.Fpga.VB_CDC7 IC K 84 Interconnect.BPI_FPGA4.Fpga.VC_TDC0 IC T 9 Interconnect.BPI_FPGA4.Fpga.VB_TDC0 IC T 10 Interconnect.BPI_FPGA4.Fpga.PullupVREF IC R 14 Interconnect.BPI_FPGA4.Fpga.PulldownVREF IC R 15 Interconnect.BPI_FPGA4.Fpga.VREF_CDC IC K 85 Interconnect.BPI_FPGA5.Fpga.Fpga IC U 6 Interconnect.BPI_FPGA5.Fpga.INIT_Pullup IC R 16 Interconnect.BPI_FPGA5.Fpga.VC_CDC0 IC K 86 Interconnect.BPI_FPGA5.Fpga.VC_CDC1 IC K 87 Interconnect.BPI_FPGA5.Fpga.VC_CDC2 IC K 88 Interconnect.BPI_FPGA5.Fpga.VC_CDC3 IC K 89 Interconnect.BPI_FPGA5.Fpga.VC_CDC4 IC K 90 Interconnect.BPI_FPGA5.Fpga.VC_CDC5 IC K 91 Interconnect.BPI_FPGA5.Fpga.VC_CDC6 IC K 92 Interconnect.BPI_FPGA5.Fpga.VC_CDC7 IC K 93 Interconnect.BPI_FPGA5.Fpga.VB_CDC0 IC K 94 Interconnect.BPI_FPGA5.Fpga.VB_CDC1 IC K 95 Interconnect.BPI_FPGA5.Fpga.VB_CDC2 IC K 96 Interconnect.BPI_FPGA5.Fpga.VB_CDC3 IC K 97 Interconnect.BPI_FPGA5.Fpga.VB_CDC4 IC K 98 Interconnect.BPI_FPGA5.Fpga.VB_CDC5 IC K 99 Interconnect.BPI_FPGA5.Fpga.VB_CDC6 IC K 100 Interconnect.BPI_FPGA5.Fpga.VB_CDC7 IC K 101 Interconnect.BPI_FPGA5.Fpga.VC_TDC0 IC T 11 Interconnect.BPI_FPGA5.Fpga.VB_TDC0 IC T 12 Interconnect.BPI_FPGA5.Fpga.PullupVREF IC R 17 Interconnect.BPI_FPGA5.Fpga.PulldownVREF IC R 18 Interconnect.BPI_FPGA5.Fpga.VREF_CDC IC K 102 Interconnect.TTC_FPGA.Fpga.Fpga IC U 7 Interconnect.TTC_FPGA.Fpga.INIT_Pullup IC R 19 Interconnect.TTC_FPGA.Fpga.VC_CDC0 IC K 103 Interconnect.TTC_FPGA.Fpga.VC_CDC1 IC K 104 Interconnect.TTC_FPGA.Fpga.VC_CDC2 IC K 105 Interconnect.TTC_FPGA.Fpga.VC_CDC3 IC K 106 Interconnect.TTC_FPGA.Fpga.VC_CDC4 IC K 107 Interconnect.TTC_FPGA.Fpga.VC_CDC5 IC K 108 Interconnect.TTC_FPGA.Fpga.VC_CDC6 IC K 109 Interconnect.TTC_FPGA.Fpga.VC_CDC7 IC K 110 Interconnect.TTC_FPGA.Fpga.VB_CDC0 IC K 111 Interconnect.TTC_FPGA.Fpga.VB_CDC1 IC K 112 Interconnect.TTC_FPGA.Fpga.VB_CDC2 IC K 113 Interconnect.TTC_FPGA.Fpga.VB_CDC3 IC K 114 Interconnect.TTC_FPGA.Fpga.VB_CDC4 IC K 115 Interconnect.TTC_FPGA.Fpga.VB_CDC5 IC K 116 Interconnect.TTC_FPGA.Fpga.VB_CDC6 IC K 117 Interconnect.TTC_FPGA.Fpga.VB_CDC7 IC K 118 Interconnect.TTC_FPGA.Fpga.VC_TDC0 IC T 13 Interconnect.TTC_FPGA.Fpga.VB_TDC0 IC T 14 Interconnect.TTC_FPGA.Fpga.PullupVREF IC R 20 Interconnect.TTC_FPGA.Fpga.PulldownVREF IC R 21 Interconnect.TTC_FPGA.Fpga.VREF_CDC IC K 119 Interconnect.TTC_FPGA.TempSensor0 IC U 8 Interconnect.TTC_FPGA.TempSensor1 IC U 9 Interconnect.TTC_FPGA.TempSensor2 IC U 10 Interconnect.TTC_FPGA.PullupTemp0 IC R 22 Interconnect.TTC_FPGA.PullupTemp1 IC R 23 Interconnect.TTC_FPGA.PullupTemp2 IC R 24 Interconnect.Rcv_FP_TTC IC U 11 Interconnect.STerm_FP_TTC0 IC R 25 Interconnect.STerm_FP_TTC1 IC R 26 Interconnect.PullupTMP_N IC R 27 Interconnect.Rcv_FP_VC_CDC IC K 120 JTAG.Buf_Emulator JT U 1 JTAG.Buf_JTAG JT U 2 JTAG.Drv_ETCK.Drv JT U 3 JTAG.Drv_ETCK.Term1 JT RP 1 JTAG.Drv_ETCK.Term2 JT RP 2 JTAG.Drv_JTCK.Drv JT U 4 JTAG.Drv_JTCK.Term1 JT RP 3 JTAG.Drv_JTCK.Term2 JT RP 4 JTAG.Drv_CCLK.Drv JT U 5 JTAG.Drv_CCLK.Term1 JT RP 5 JTAG.Drv_CCLK.Term2 JT RP 6 JTAG.STerm_ETCK JT R 1 JTAG.STerm_JTCK JT R 2 JTAG.Pull_E0 JT R 3 JTAG.Pull_E1 JT R 4 JTAG.Pull_E2 JT R 5 JTAG.Pull_E3 JT R 6 JTAG.Pull_E4 JT R 7 JTAG.Pull_E5 JT R 8 JTAG.Pull_J0 JT R 9 JTAG.Pull_J1 JT R 10 JTAG.Pull_J2 JT R 11 JTAG.Pull_J3 JT R 12 JTAG.Pull_J4 JT R 13 JTAG.Mux_JTMS JT U 6 JTAG.Mux_JTDO JT U 7 JTAG.MB_JTAG_Short JT H 1 JTAG.STerm_CCLK JT R 14 JTAG.Mono0 JT MP 1 JTAG.Mono1 JT MP 2 JTAG.Mono2 JT MP 3 JTAG.Mono3 JT MP 4 JTAG.Mono4 JT MP 5 JTAG.Mono5 JT MP 6 JTAG.Mono6 JT MP 7 JTAG.Mono7 JT MP 8 JTAG.Mono8 JT MP 9 JTAG.Mono9 JT MP 10 JTAG.Mono10 JT MP 11 JTAG.Mono11 JT MP 12 JTAG.Mono12 JT MP 13 JTAG.Mono13 JT MP 14 JTAG.Mono14 JT MP 15 JTAG.Mono15 JT MP 16 JTAG.Mono16 JT MP 17 JTAG.Mono17 JT MP 18 JTAG.Mono18 JT MP 19 JTAG.E_CDC0 JT K 1 JTAG.E_CDC1 JT K 2 JTAG.E_CDC2 JT K 3 JTAG.E_CDC3 JT K 4 JTAG.E_CDC4 JT K 5 JTAG.E_CDC5 JT K 6 JTAG.E_CDC6 JT K 7 JTAG.E_CDC7 JT K 8 JTAG.J_CDC0 JT K 9 JTAG.J_CDC1 JT K 10 JTAG.J_CDC2 JT K 11 JTAG.J_CDC3 JT K 12 JTAG.J_CDC4 JT K 13 JTAG.J_CDC5 JT K 14 JTAG.J_CDC6 JT K 15 JTAG.J_CDC7 JT K 16 JTAG.J_CDC8 JT K 17 JTAG.J_CDC9 JT K 18 JTAG.J_CDC10 JT K 19 JTAG.J_CDC11 JT K 20 JTAG.J_CDC12 JT K 21 JTAG.J_CDC13 JT K 22 JTAG.E_TDC0 JT T 1 JTAG.E_TDC1 JT T 2 JTAG.J_TDC0 JT T 3 Power.AuxPower PW H 1 Power.Pulldown0 PW R 1 Power.Pulldown1 PW R 2 Power.Pulldown2 PW R 3 Power.Pulldown3 PW R 4 Power.Pulldown4 PW R 5 Power.SeriesVPC PW R 6 Power.Raux_VPC PW R 7 Power.LatchSwitch PW H 2 Power.LatchOverride PW H 3 Power.Super_VCOK.Supr PW U 1 Power.Super_VCOK.Rsense1 PW R 8 Power.Super_VCOK.CDC PW K 1 Power.Super_MBPWROK.Supr PW U 2 Power.Super_MBPWROK.Rsense1 PW R 9 Power.Super_MBPWROK.CDC PW K 2 Power.Super_VINOK.Supr PW U 3 Power.Super_VINOK.Rsense1 PW R 10 Power.Super_VINOK.CDC PW K 3 Power.Super_ONE.Supr PW U 4 Power.Super_ONE.Rsense1 PW R 11 Power.Super_ONE.CDC PW K 4 Power.Comp_VAOK.Reference PW U 5 Power.Comp_VAOK.Rb PW R 12 Power.Comp_VAOK.Rrefh PW R 13 Power.Comp_VAOK.Rrefl PW R 14 Power.Comp_VAOK.Rh PW R 15 Power.Comp_VAOK.RAdjust PW R 16 Power.Comp_VAOK.Amp PW U 6 Power.Comp_VBOK.Reference PW U 7 Power.Comp_VBOK.Rb PW R 17 Power.Comp_VBOK.Rrefh PW R 18 Power.Comp_VBOK.Rrefl PW R 19 Power.Comp_VBOK.Rh PW R 20 Power.Comp_VBOK.RAdjust PW R 21 Power.Comp_VBOK.Amp PW U 8 Power.DCDC_DSP_VA.Regulator PW U 9 Power.DCDC_DSP_VA.R_VID0 PW R 22 Power.DCDC_DSP_VA.R_VID1 PW R 23 Power.DCDC_DSP_VA.R_VID2 PW R 24 Power.DCDC_DSP_VA.R_VID3 PW R 25 Power.DCDC_DSP_VA.R_VID4 PW R 26 Power.DCDC_DSP_VA.Cin0 PW C 1 Power.DCDC_DSP_VA.Cin1 PW C 2 Power.DCDC_DSP_VA.Cin2 PW C 3 Power.DCDC_DSP_VA.Cin3 PW C 4 Power.DCDC_DSP_VA.Cin4 PW C 5 Power.DCDC_DSP_VA.Cin5 PW C 6 Power.DCDC_DSP_VA.Cout PW C 7 Power.DCDC_DSP_VA.Rsense0 PW R 27 Power.DCDC_DSP_VA.Rsense1 PW R 28 Power.DCDC_VB.Regulator PW U 10 Power.DCDC_VB.R_VID0 PW R 29 Power.DCDC_VB.R_VID1 PW R 30 Power.DCDC_VB.R_VID2 PW R 31 Power.DCDC_VB.R_VID3 PW R 32 Power.DCDC_VB.R_VID4 PW R 33 Power.DCDC_VB.Cin0 PW C 8 Power.DCDC_VB.Cin1 PW C 9 Power.DCDC_VB.Cin2 PW C 10 Power.DCDC_VB.Cin3 PW C 11 Power.DCDC_VB.Cin4 PW C 12 Power.DCDC_VB.Cin5 PW C 13 Power.DCDC_VB.Cout PW C 14 Power.DCDC_VB.Rsense0 PW R 34 Power.DCDC_VB.Rsense1 PW R 35 Power.OVP_MB_VCC5.Reference PW U 11 Power.OVP_MB_VCC5.Rb PW R 36 Power.OVP_MB_VCC5.Rh PW R 37 Power.OVP_MB_VCC5.Radjust PW R 38 Power.OVP_MB_VCC5.Ro PW R 39 Power.OVP_MB_VCC5.Co PW C 15 Power.OVP_MB_VCC5.Amp PW U 12 Power.OVP_MB_VCC5.Dprotect PW D 1 Power.OVP_MB_VCC5.SCR PW Q 1 Power.OVP_MB_VCC.Reference PW U 13 Power.OVP_MB_VCC.Rb PW R 40 Power.OVP_MB_VCC.Rh PW R 41 Power.OVP_MB_VCC.Radjust PW R 42 Power.OVP_MB_VCC.Ro PW R 43 Power.OVP_MB_VCC.Co PW C 16 Power.OVP_MB_VCC.Amp PW U 14 Power.OVP_MB_VCC.Dprotect PW D 2 Power.OVP_MB_VCC.SCR PW Q 2 Power.OVP_DSP_VCC.Reference PW U 15 Power.OVP_DSP_VCC.Rb PW R 44 Power.OVP_DSP_VCC.Rh PW R 45 Power.OVP_DSP_VCC.Radjust PW R 46 Power.OVP_DSP_VCC.Ro PW R 47 Power.OVP_DSP_VCC.Co PW C 17 Power.OVP_DSP_VCC.Amp PW U 16 Power.OVP_DSP_VCC.Dprotect PW D 3 Power.OVP_DSP_VCC.SCR PW Q 3 Power.OVP_DSP_VA.Reference PW U 17 Power.OVP_DSP_VA.Rb PW R 48 Power.OVP_DSP_VA.Rh PW R 49 Power.OVP_DSP_VA.Radjust PW R 50 Power.OVP_DSP_VA.Ro PW R 51 Power.OVP_DSP_VA.Co PW C 18 Power.OVP_DSP_VA.Amp PW U 18 Power.OVP_DSP_VA.Dprotect PW D 4 Power.OVP_DSP_VA.SCR0 PW Q 4 Power.OVP_DSP_VA.SCR1 PW Q 5 Power.OVP_DSP_VA.SCR2 PW Q 6 Power.OVP_VB.Reference PW U 19 Power.OVP_VB.Rb PW R 52 Power.OVP_VB.Rh PW R 53 Power.OVP_VB.Radjust PW R 54 Power.OVP_VB.Ro PW R 55 Power.OVP_VB.Co PW C 19 Power.OVP_VB.Amp PW U 20 Power.OVP_VB.Dprotect PW D 5 Power.OVP_VB.SCR0 PW Q 7 Power.OVP_VB.SCR1 PW Q 8 Power.OVP_VB.SCR2 PW Q 9 Power.OVP_SW5_VB.Reference PW U 21 Power.OVP_SW5_VB.Rb PW R 56 Power.OVP_SW5_VB.Rh PW R 57 Power.OVP_SW5_VB.Radjust PW R 58 Power.OVP_SW5_VB.Ro PW R 59 Power.OVP_SW5_VB.Co PW C 20 Power.OVP_SW5_VB.Amp PW U 22 Power.OVP_SW5_VB.Dprotect PW D 6 Power.OVP_SW5_VB.SCR0 PW Q 10 Power.OVP_SW5_VB.SCR1 PW Q 11 Power.OVP_SW5_DVA.Reference PW U 23 Power.OVP_SW5_DVA.Rb PW R 60 Power.OVP_SW5_DVA.Rh PW R 61 Power.OVP_SW5_DVA.Radjust PW R 62 Power.OVP_SW5_DVA.Ro PW R 63 Power.OVP_SW5_DVA.Co PW C 21 Power.OVP_SW5_DVA.Amp PW U 24 Power.OVP_SW5_DVA.Dprotect PW D 7 Power.OVP_SW5_DVA.SCR0 PW Q 12 Power.OVP_SW5_DVA.SCR1 PW Q 13 Power.Measure.Regulator PW U 25 Power.Measure.Reference1 PW U 26 Power.Measure.Reference2 PW U 27 Power.Measure.Reference3 PW U 28 Power.Measure.Mux PW U 29 Power.Measure.ADC PW U 30 Power.Measure.Buffer1 PW U 31 Power.Measure.Buffer2 PW U 32 Power.Measure.Rpwr1 PW R 64 Power.Measure.Rpwr2 PW R 65 Power.Measure.Rb PW R 66 Power.Measure.Rin1 PW R 67 Power.Measure.Rfb1 PW R 68 Power.Measure.Rfb2 PW R 69 Power.Measure.Rdivh PW R 70 Power.Measure.Rdivl PW R 71 Power.Measure.Rsclkp PW R 72 Power.Measure.Rclkp PW R 73 Power.Measure.Rsclks PW R 74 Power.Measure.Rclks PW R 75 Power.Measure.Rdouts PW R 76 Power.Measure.Rmuxin0 PW R 77 Power.Measure.Rmuxin1 PW R 78 Power.Measure.Rmuxin2 PW R 79 Power.Measure.Rmuxin3 PW R 80 Power.Measure.Rmuxin4 PW R 81 Power.Measure.Rmuxin5 PW R 82 Power.Measure.Rmuxin6 PW R 83 Power.Measure.Rmuxin7 PW R 84 Power.Measure.Rmuxin8 PW R 85 Power.Measure.Rmuxin9 PW R 86 Power.Measure.Rmuxin10 PW R 87 Power.Measure.Rmuxin11 PW R 88 Power.Measure.Rmuxin12 PW R 89 Power.Measure.Rmuxin13 PW R 90 Power.Measure.Rmuxin14 PW R 91 Power.Measure.Rmuxin15 PW R 92 Power.Measure.Rpwr3 PW R 93 Power.Measure.CDC0 PW K 5 Power.Measure.CDC1 PW K 6 Power.Measure.CDC2 PW K 7 Power.Measure.CDC3 PW K 8 Power.Measure.CDC4 PW K 9 Power.Measure.CDC5 PW K 10 Power.Measure.CDC6 PW K 11 Power.Measure.TDC PW T 1 Power.SW_DSP_VCC.Dprotect PW D 8 Power.SW_DSP_VCC.CapI PW K 12 Power.SW_DSP_VCC.CapO PW K 13 Power.SW_DSP_VCC.Switch0 PW U 33 Power.SW_DSP_VCC.Switch1 PW U 34 Power.SW_DSP_VCC.Switch2 PW U 35 Power.SW_DSP_VCC.Switch3 PW U 36 Power.SW_MB_VCC.Dprotect PW D 9 Power.SW_MB_VCC.CapI PW K 14 Power.SW_MB_VCC.CapO PW K 15 Power.SW_MB_VCC.Switch0 PW U 37 Power.SW_MB_VCC.Switch1 PW U 38 Power.SW_MB_VCC.Switch2 PW U 39 Power.SW_MB_VCC.Switch3 PW U 40 Power.SW_MB_VCC5.Dprotect PW D 10 Power.SW_MB_VCC5.CapI PW K 16 Power.SW_MB_VCC5.CapO PW K 17 Power.SW_MB_VCC5.Switch0 PW U 41 Power.SW_MB_VCC5.Switch1 PW U 42 Power.SW_DSP_VA.Dprotect PW D 11 Power.SW_DSP_VA.CapI PW K 18 Power.SW_DSP_VA.CapO PW K 19 Power.SW_DSP_VA.Switch0 PW U 43 Power.SW_DSP_VA.Switch1 PW U 44 Power.SW_DSP_VA.Switch2 PW U 45 Power.SW_DSP_VA.Switch3 PW U 46 Power.SW_DSP_VA.Switch4 PW U 47 Power.SW_VB.Dprotect PW D 12 Power.SW_VB.CapI PW K 20 Power.SW_VB.CapO PW K 21 Power.SW_VB.Switch0 PW U 48 Power.SW_VB.Switch1 PW U 49 Power.SW_VB.Switch2 PW U 50 Power.SW_VB.Switch3 PW U 51 Power.SW_VB_SURGE.Dprotect PW D 13 Power.SW_VB_SURGE.CapI PW K 22 Power.SW_VB_SURGE.CapO PW K 23 Power.SW_VB_SURGE.Switch0 PW U 52 Power.SW_VB_SURGE.Switch1 PW U 53 Power.Mono0 PW MP 1 Power.Mono1 PW MP 2 Power.Mono2 PW MP 3 Power.Mono3 PW MP 4 VME_Interface.buffers.DataBuffer15_00 VM U 1 VME_Interface.buffers.DataBuffer31_16 VM U 2 VME_Interface.buffers.AddrBuffer15_01 VM U 3 VME_Interface.buffers.AddrBuffer23_16 VM U 4 VME_Interface.buffers.AddrBuffer31_24 VM U 5 VME_Interface.buffers.CntlBuffer1 VM U 6 VME_Interface.buffers.CntlBuffer2 VM U 7 VME_Interface.buffers.InptBuffer VM U 8 VME_Interface.buffers.VPC_Res_AddrBuf VM R 1 VME_Interface.buffers.VPC_Res_DataBuf VM R 2 VME_Interface.buffers.VPC_Res_InptBuf VM R 3 VME_Interface.buffers.OE_Res_AddrBuf VM R 4 VME_Interface.buffers.OE_Res_DataBuf VM R 5 VME_Interface.buffers.OE_Res_InptBuf VM R 6 VME_Interface.buffers.Pullup_DIR_InptBuf VM R 7 VME_Interface.buffers.Pulldown_DIR_InptBuf VM R 8 VME_Interface.buffers.Pullup_OE_AddrBuf VM R 9 VME_Interface.buffers.Pullup_OE_DataBuf VM R 10 VME_Interface.buffers.Pullup_OE_InptBuf VM R 11 VME_Interface.buffers.Pullup_IACKOUT VM R 12 VME_Interface.buffers.Pullup_CtrlBuf1 VM RP 1 VME_Interface.buffers.Pullup_CtrlBuf2 VM RP 2 VME_Interface.VMEC_PLD.Cpld VM U 9 VME_Interface.VMED_PLD.Cpld VM U 10 VME_Interface.VME_FIFO.Fifo VM U 11 VME_Interface.VME_FIFO.VC_CDC0 VM K 1 VME_Interface.VME_FIFO.VC_CDC1 VM K 2 VME_Interface.VME_FIFO.VC_CDC2 VM K 3 VME_Interface.VME_FIFO.VC_CDC3 VM K 4 VME_Interface.VME_FIFO.VC_CDC4 VM K 5 VME_Interface.VME_FIFO.VC_CDC5 VM K 6 VME_Interface.VME_FIFO.VC_CDC6 VM K 7 VME_Interface.VME_FIFO.VC_CDC7 VM K 8 VME_Interface.VME_FIFO.VC_CDC8 VM K 9 VME_Interface.VME_FIFO.VC_CDC9 VM K 10 VME_Interface.VME_FIFO.VC_CDC10 VM K 11 VME_Interface.VME_FIFO.VC_TDC0 VM T 1 VME_Interface.VME_DPR VM U 12 VME_Interface.FlashPLD.Cpld VM U 13 VME_Interface.BootFlash VM U 14 VME_Interface.CR_Flash VM U 15 VME_Interface.PulldownDPRAM_Data VM RP 3 VME_Interface.PullupDIPSW0 VM RP 4 VME_Interface.PullupDIPSW1 VM RP 5 VME_Interface.PullupDIPSW2 VM RP 6 VME_Interface.PullupDIPSW3 VM RP 7 VME_Interface.VCC_CDC0 VM K 12 VME_Interface.VCC_CDC1 VM K 13 VME_Interface.VCC_CDC2 VM K 14 VME_Interface.VCC_CDC3 VM K 15 VME_Interface.VCC_CDC4 VM K 16 VME_Interface.VCC_CDC5 VM K 17 VME_Interface.VCC_CDC6 VM K 18 VME_Interface.VCC_CDC7 VM K 19 VME_Interface.VCC_CDC8 VM K 20 VME_Interface.VCC_CDC9 VM K 21 VME_Interface.VCC_CDC10 VM K 22 VME_Interface.VCC_CDC11 VM K 23 VME_Interface.VCC_CDC12 VM K 24 VME_Interface.VCC_CDC13 VM K 25 VME_Interface.VCC_CDC14 VM K 26 VME_Interface.VCC_CDC15 VM K 27 VME_Interface.VCC_CDC16 VM K 28 VME_Interface.VCC_CDC17 VM K 29 VME_Interface.VCC_CDC18 VM K 30 VME_Interface.VCC_CDC19 VM K 31 VME_Interface.VCC_CDC20 VM K 32 VME_Interface.VCC5_CDC0 VM K 33 VME_Interface.VCC5_CDC1 VM K 34 VME_Interface.VCC5_CDC2 VM K 35 VME_Interface.VCC5_CDC3 VM K 36 VME_Interface.VCC5_CDC4 VM K 37 VME_Interface.VCC5_CDC5 VM K 38 VME_Interface.VCC5_CDC6 VM K 39 VME_Interface.VCC5_CDC7 VM K 40 VME_Interface.VCC5_CDC8 VM K 41 VME_Interface.VCC5_CDC9 VM K 42 VME_Interface.VCC5_CDC10 VM K 43 VME_Interface.VCC5_CDC11 VM K 44 VME_Interface.VCC5_CDC12 VM K 45 VME_Interface.VCC5_CDC13 VM K 46 VME_Interface.VCC5_CDC14 VM K 47 VME_Interface.VCC5_CDC15 VM K 48 VME_Interface.VCC5_CDC16 VM K 49 VME_Interface.VCC5_CDC17 VM K 50 VME_Interface.VCC5_CDC18 VM K 51 VME_Interface.VCC5_CDC19 VM K 52 VME_Interface.VCC5_CDC20 VM K 53 VME_Interface.VCC5_CDC21 VM K 54 VME_Interface.VCC5_CDC22 VM K 55 VME_Interface.VCC5_CDC23 VM K 56 VME_Interface.VCC5_CDC24 VM K 57 VME_Interface.VCC5_CDC25 VM K 58 VME_Interface.VCC_TDC0 VM T 2 VME_Interface.VCC_TDC1 VM T 3 VME_Interface.VCC5_TDC0 VM T 4 VME_Interface.VCC5_TDC1 VM T 5 VME_Interface.VCC5_TDC2 VM T 6 VME_Interface.CR_CDC0 VM K 59 VME_Interface.CR_CDC1 VM K 60